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| Discontinued - v3.0 v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families F ea t u re s H ig h C a p ac it y G e n e ra l D es c ri p t i o n * * * * * * * * 2,500 to 30,000 Logic Gates Up to 3Kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 250 User-Programmable I/O Pins 225 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode H ig h P e r f o r m a nc e Actel's Integrator Series FPGAs are the first programmable logic devices optimized for high-speed system logic integration. Based on Actel's proprietary antifuse technology and 0.6-micron double metal CMOS process, Integrator Series devices offer a fine-grained, register-rich architecture with embedded dual-port SRAM and wide-decode circuitry. Integrator Series' 3200DX and 1200XL families were designed to integrate system logic which is typically implemented in multiple CPLDs, PALs, and FPGAs. These devices provide the features and performance required for today's complex, high-speed digital logic systems. The 3200DX family offers fast dual-port SRAM for implementing FIFOs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide datapath manipulation and transformation functions such as telecommunications, networking, and DSP. E a s e - of -I n t e g r a t i o n * Synthesis-Friendly Architecture Supports ASIC Design Methodologies. * 95-100% Device Utilization using Automatic Place-and-Route Tools. * Deterministic, User-Controllable Timing Via Timing Driven Software Tools with Up To 100% Pin Fixing. * IEEE Standard 1149.1 (JTAG) Boundary Scan Testing. In t eg r a to r S e ri e s P ro d u ct P r of i l e F a m i l y 1200XL Device A1225XL 2,500 N/A 231 220 N/A N/A 231 2 83 No A1240XL 4,000 N/A 348 336 N/A N/A 348 2 104 No A1280XL 8,000 N/A 624 608 N/A N/A 624 2 140 No 3200DX A3265DX 6,500 N/A 510 475 20 N/A 510 2 126 No PL84 PQ100 PQ160 TQ176 A32100DX 10,000 2,048 700 662 20 8 700 6 152 Yes PL84 PQ160 PQ208 TQ176 CQ84 A32140DX 14,000 N/A 954 912 24 N/A 954 2 176 Yes PL84 PQ160 PQ208 TQ176 CQ256 A32200DX 20,000 2,560 1,230 1,184 24 10 1,230 6 202 Yes PQ208 RQ208 RQ240 CQ208 CQ256 A32300DX 30,000 3,072 1,888 1,833 28 12 1,888 6 250 Yes RQ208 RQ240 CQ256 Capacity Logic Gates1 SRAM Bits Sequential Combinatorial Decode Logic Modules SRAM Modules (64x4 or 32x8) Dedicated Flip-Flops Clocks User I/O (Maximum) JTAG Packages PL84 PQ100 VQ100 PG100 PL84 PQ100 PQ144 TQ176 PG132 PL84 PQ160 PQ208 TQ176 PG176 CQ172 Note: Logic gate capacity does not include SRAM bits as logic. February 2001 1 (c) 2001 Actel Corporation I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s O r d er i n g In f or m a t i o n A1225 XL V - PQ 100 C Application (Temperature Range) C = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 Package Lead Count Package Type CQ = Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack RQ = Plastic Power Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard 3 = Approximately 35% Faster than Standard F = Approximately 30% Slower than Standard Operating Voltage V = 3.3 Volt Blank = 5.0 Volt Die Revision XL = 1200XL Family DX = 3200DX Family Part Number A1225 A1240 A3265 A1280 A32100 A32140 A32200 A32300 = = = = = = = = 2500 Gates 4000 Gates 6500 Gates 8000 Gates 10000 Gates 14000 Gates 20000 Gates 30000 Gates Note: This family has been discontinued. 2 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ro d u ct P l a n Speed Grade* -F A1225XL Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 100-Pin Ceramic Pin Grid Array (CPGA) A1225XLV Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A1240XL Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 132-Pin Ceramic Pin Grid Array (CPGA) 144-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A1240XLV Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A3265DX Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A3265DXV Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A1280XL Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 160-Pin Plastic Quad Flat Pack (PQFP) 172-Pin Ceramic Quad Flat Pack (CQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 176-Pin Ceramic Pin Grid Array (CPGA) 208-Pin Plastic Quad Flat Pack (PQFP) A1280XLV Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A32100DX Device 84-Pin Ceramic Quad Flat Pack (CQFP) 84-Pin Plastic Leaded Chip Carrier (PLCC) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) -- -- -- -- -- -- -- -- -- Std -1 -2 -3 C Application I M B -- -- -- -- -- -- -- -- -- = = = = -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -1 -2 -3 -F Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available *Speed Grade: I = Industrial P = Planned M = Military -- = Not Planned Approx. 15% faster than Standard Approx. 25% faster than Standard Approx. 35% faster than Standard Approx. 40% slower than Standard Only Std, -1, -2 Speed Grade * Only Std, -1 Speed Grade Discontinued - v3.0 3 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F am i l i e s P ro d u ct P l a n (Continued) Speed Grade* -F 176-Pin Thin Plastic Quad Flat Pack (TQFP) A32100DXV Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A32140DX Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 160-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A32140DXV Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A32200DX Device 208-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Power Quad Flat Pack (RQFP) 240-Pin Plastic Power Quad Flat Pack (RQFP) 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A32200DXV Device 208-Pin Plastic Quad Flat Pack (PQFP) 240-Pin Plastic Power Quad Flat Pack (RQFP) A32300DX Device 208-Pin Plastic Power Quad Flat Pack (RQFP) 240-Pin Plastic Power Quad Flat Pack (RQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A32300DXV Device 208-Pin Plastic Power Quad Flat Pack (RQFP) 240-Pin Plastic Power Quad Flat Pack (RQFP) -- -- -- -- -- -- -- -- Std -1 -2 -3 C Application I M -- B -- -- -- -- -- -- -- = = = = -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available *Speed Grade: I = Industrial P = Planned M = Military -- = Not Planned -1 -2 -3 -F Approx. 15% faster than Standard Approx. 25% faster than Standard Approx. 35% faster than Standard Approx. 40% slower than Standard Only Std, -1, -2 Speed Grade * Only Std, -1 Speed Grade 4 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s D e v e l o p m e n t T o o l S u p po r t The devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer Advantage tools. The Actel DeskTOP series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place and route tools. Designer Advantage, Actel's suite of FPGA development point tools for PCs and Workstations, includes the ACTgen Macro Builder, timing-driven place and route and analysis tools, and device programming software. In addition, the devices contain ActionProbe circuitry that provides built-in access to every node in a design, enabling 100 percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional P l a s t i c D e v i c e R e s ou r c es 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds. In t e gr a to r S e ri e s A r ch i t e c tu r al O v e rv i e w The 1200XL and 3200DX architecture is composed of fine-grained building blocks which produce fast, efficient logic designs. All devices within the Integrator Series are composed of logic modules, routing resources, clock networks, and I/O modules which are the building blocks to design fast logic designs. In addition, a subset of devices contain embedded dual-port SRAM and wide-decode modules. The dual-port SRAM modules are optimized for high-speed datapath functions such as FIFOs, LIFOs, and scratchpad memory. The "Integrator Series Product Profile Family" on page 1 lists the specific logic resources contained within each device. User I/Os Device A1225XL A1240XL A3265DX A1280XL A32100DX A32140DX A32200DX A32300DX PLCC 84-Pin 72 72 72 72 72 72 -- -- VQFP 100-Pin 83 -- -- -- -- -- -- -- PQFP 100-Pin 83 83 83 -- -- -- -- -- PQFP 144-Pin PQFP 160-Pin PQFP 208-Pin -- 104 -- -- -- -- -- -- -- -- 125 125 125 125 -- -- -- -- -- 140 152 176 176* 176 RQFP 240-Pin -- -- -- -- -- -- 202 202 TQFP 176-Pin -- 103 126 140 142 150 -- -- Package Definitions (Consult your local Actel Sales Representative for product availability.) PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array, VQFP = Very Thin Quad Flat Pack, RQFP = Plastic Power Quad Flat Pack * Also available in RQFP 208-pin. H e r m e ti c D ev i c e R e s o u rc e s User I/Os Device A1280XL A32100DX A32140DX A32200DX A32300DX CPGA 176-Pin 140 -- -- -- -- CQFP 84-Pin -- 60 -- -- -- CQFP 172-Pin 140 -- -- -- -- CQFP 208-Pin -- -- -- 176 -- CQFP 256-Pin -- -- 176 202 212 Package Definitions (Consult your local Actel Sales Representative for product availability.) CPGA = Ceramic Pin Grid Array, CQFP = Ceramic Quad Flat Pack Discontinued - v3.0 5 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s Lo g i c M o du l e s 3200DX and 1200XL devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules), and decode (D-modules). 1200XL devices contain only the C-module and S-module, while the 3200DX devices contain D-modules and dual-port SRAM modules in addition to the S-module and C-module. The C-module is shown in Figure 1 and implements the following function: Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11 where: S0=A0*B0 S1=A1+B1 The S-module shown in Figure 2 is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-type flip-flop or a transparent latch. To increase flexibility, the S-module register can be bypassed so that it implements purely combinatorial logic. A0 B0 S0 D00 D01 D10 D11 S1 A1 B1 Y Figure 1 * C-Module Implementation D00 D01 D10 D11 S1 Y S0 CLR D Q OUT D00 D01 D10 D11 S1 Y S0 D GATE Q OUT Up to 7-Input Function Plus D-Type Flip-Flop with Clear Up to 7-Input Function Plus Latch D00 D0 Y D1 S D GATE CLR Q OUT D01 D10 D11 S1 S0 Y OUT Up to 4-Input Function Plus Latch with Clear Up to 8-Input Function (Same as C-Module) Figure 2 * S-Module Implementation 6 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 3200DX devices contain a third type of logic module, D-modules, which are arranged around the periphery of the device. D-modules contain wide-decode circuitry which provides a fast, wide-input AND function similar to that found in product term architectures (Figure 3). The D-module allows 3200DX devices to perform wide-decode functions at speeds comparable CPLDs and PAL devices. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hard-wired to an output pin or can be fed back into the array to be incorporated into other logic. Dual-Port SRAM Modules modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the 3200DX dual-port SRAM block is shown in Figure 4. 7 Inputs Hard-Wire to I/O Programmable Inverter Several 3200DX devices contain dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks which can be configured as 32x8 or 64x4 (refer to "Integrator Series Product Profile Family" on page 1 for the number of SRAM blocks within a particular device). SRAM Feedback to Array Figure 3 * D-Module Implementation WD[7:0] Latches [7:0] [5:0] Write Port Logic SRAM Module 32 x 8 or 64 x 4 (256 Bits) Read Port Logic Latches RDAD[5:0] WRAD[5:0] Latches [5:0] Read Logic REN RCLK MODE BLKEN WEN WCLK Write Logic RD[7:0] Routing Tracks Figure 4 * 3200DX Dual-Port SRAM Block The 3200DX SRAM modules are true dual-port structures containing independent READ and WRITE ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4 bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]) and eight outputs (RD[7:0]) which are connected to segmented vertical routing tracks. The 3200DX dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring fast FIFO and LIFO queues. Actel's ACTgen Macro Builder provides the capability to quickly design memory functions, Discontinued - v3.0 7 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s such as FIFOs, LIFOs, and RAM arrays. Additionally, unused SRAM blocks can be used to implement registers for other logic within the design. I/O Modules be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Horizontal Routing The I/O modules provide the interface between the device pins and the logic array. Figure 5 is a block diagram of the I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module (refer to the Macro Library Guide for more information). I/O modules contain a tri-state buffer, input and output latches which can be configured for input, output, or bi-directional pins (Figure 5). EN Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 6. Non-dedicated horizontal routing tracks are used to route signal nets; dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing Q From Array D PAD G/CLK* Q To Array D G/CLK* * Can be Configured as a Latch or D Flip-Flop (Using C-Module) Another set of routing tracks run vertically through the module. Vertical tracks are of three types: input, output, and long, and are divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. Long Vertical Tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 6. Figure 5 * I/O Module The Integrator Series devices contain flexible I/O structures where each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast set-up time. In addition, the Actel Designer Series software tools can build a D-type flip-flop using a C-module to register input and/or output signals. Actel's Designer Series development tools provide a design library of I/O macrofunctions which can implement all I/O configurations supported by the Integrator Series FPGAs. Routing Structure Segmented Horizontal Routing Tracks Logic Modules Antifuses Vertical Routing Tracks The Integrator Series architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into pieces called segments. Varying segment lengths allows interconnection of over 90% of design tracks to occur with only two antifuse connections. Segments can Figure 6 * Routing Structure A n t i f us e S t r u c t u r e An antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly-testable structures as well as efficient 8 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s programming algorithms. The structure is highly testable because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Clock Networks CLKB CLKA From Pads CLKMOD CLKINB CLKINA S0 S1 Internal Signal CLKO(17) Clock Drivers CLKO(16) CLKO(15) Two low-skew, high-fanout clock distribution networks are provided in each 3200DX device. These networks are referred to as CLK0 and CLK1. Each network has a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows: 1. 2. 3. 4. Externally from the CLKA pad Externally from the CLKB pad Internally from the CLKINA input Internally from the CLKINB input Figure 7 * Clock Networks CLKO(2) CLKO(1) Clock Tracks The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The user controls the clock module by selecting one of two clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally-generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. The clock input pads may also be used as normal I/Os, bypassing the clock networks (see Figure 7). The 3200DX devices which contain SRAM modules (all except A3265DX and A32140DX) have four additional register control resources, called quadrant clock networks (Figure 8 on page 10). Each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. Test Circuitry IEEE Standard 1149.1 Boundary Scan Testing (BST) IEEE Standard 1149.1 defines a four-pin Test Access Port (TAP) interface for testing integrated circuits in a system. The 3200DX family provides five BST pins: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), and Test Mode Select Test Reset (TRST) (3200DX24A only). Devices are configured in a test "chain" where BST data can be transmitted serially between devices via TDO-to-TDI interconnections. The TMS and TCK signals are shared among all devices in the test chain so that all components operate in the same state. The 3200DX family implements a subset of the IEEE Standard 1149.1 BST instruction in addition to a private instruction, which allows the use of Actel's ActionProbe facility with BST. Refer to the IEEE Standard 1149.1 specification for detailed information regarding BST. Boundary Scan Circuitry All devices contain Actel's ActionProbe test circuitry which test and debug a design once it is programmed into a device. Once a device has been programmed, the ActionProbe test circuitry allows the designer to probe any internal node during device operation to aid in debugging a design. In addition, 3200DX devices contain IEEE Standard 1149.1 boundary scan test circuitry. The 3200DX boundary scan circuitry consists of a Test Access Port (TAP) controller, test instruction register, a JPROBE register, a bypass register, and a boundary scan register. Figure 9 on page 10 shows a block diagram of the 3200DX boundary scan circuitry. When a device is operating in BST mode, four I/O pins are used for the TDI, TDO, TMS, and TCK signals. An active reset (nTRST) pin is not supported; however, the 3200DX device contain power-on circuitry that resets the boundary scan circuitry upon power-up. Table 1 on page 11 summarizes the functions of the IEEE 1149.1 BST signals. Discontinued - v3.0 9 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s QCLKA Quad Clock Module Quad Clock Module QCLKC QCLKB *QCLK1IN QCLK1 QCLK3 QCLKD *QCLK3IN S0 S1 S1 S0 Quad Clock Module *QCLK2IN S0 S1 QCLK2 QCLK4 Quad Clock Module *QCLK4IN S1 S0 *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals. Figure 8 * Quadrant Clock Network JPROBE Register Boundary Scan Register Bypass Register Control Logic JTAG TMS TAP Controller TCK Output MUX TDO Instruction Decode JTAG TDI Instruction Register Figure 9 * 3200DX IEEE 1149.1 Boundary Scan Circuitry 10 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s Table 1 * IEEE 1149.1 BST Signals Signal Name Function Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. Serial data output for BST instructions and test data. Serial data input for BST mode. Data is shifted in on the rising edge of TCK. Clock signal to shift the BST data into the device. Table 2 * BST Instructions Test Mode Code Description Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Allows a snapshot of the signals at the device pins to be captured and examined during device operation. A private instruction allowing the user to connect Actel's Micro Probe registers to the test chain. Allows the user to build application-specific instructions such as RAM READ and RAM WRITE. Refer to the IEEE Standard 1149.1 specification. Refer to the IEEE Standard 1149.1 specification. Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the test chain. TDI Test Data In EXTEST 000 TDO TMS TCK Test Data Out Test Mode Select Test Clock SAMPLE/ PRELOAD 001 JPROBE 011 JTAG All 3200DX devices are IEEE 1149.1 (JTAG) compliant. 3200DX devices offer superior diagnostic and testing capabilities by providing JTAG and probing capabilites. These functions are controlled through the special JTAG pins in conjunction with the program fuse. JTAG fuse programmed: * TCK must be terminated--logical high or low doesn't matter (to avoid floating input) * TDI, TMS may float or at logical high (internal pull-up is present) * TDO may float or connect to TDI of another device (it's an output) JTAG fuse not programmed: * TCK, TDI, TDO, TMS are user I/O. If not used, they will be configured as tristated output. BST Instructions USER INSTRUCTION HIGH Z CLAMP 100 101 110 BYPASS 111 JTAG BST Instructions JTAG BST testing within the 3200DX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the JTAG testing of the device. The JTAG test mode is determined by the bitstream entered on the TMS pin. The table in the next column describes the JTAG instructions supported by the 3200DX. Design Tool Support ActionProbe Boundary scan testing within the 3200DX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the testing of the device. The BST mode is determined by the bitstream entered on the TMS pin. Table 2 describes the test instructions supported by the 3200DX devices. Reset If a device has been successfully programmed and the security fuse has not been programmed, any internal logic or I/O module output can be observed in real time using the ActionProbe circuitry, the PRA and/or PRB pins, and Actel's Silicon Explorer diagnostic and debug tool kit. The TMS pin is equipped with an internal pull-up resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five TCK cycles. When a device is operating in BST mode, four I/O pins are used for the TDI, TDO, TMS, and TCLK signals. An active reset (nTRST) pin is not supported; however, the 3200DX contains power-on circuitry which automatically resets the BST circuitry upon power-up. The following table summarizes the functions of the BST signals. Discontinued - v3.0 11 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 5 . 0V O p e ra t i n g C o n di t i o n s A b s o l u t e Ma x i m u m R a ti n g s 1 Fre e A ir Te m p er a t u re R an ge Symbol VCC VI2 VO TSTG Parameter DC Supply Voltage Input Voltage Output Voltage Storage Temperature Limits -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 Units V V V C R e c o m m e n de d O p e r at i n g C o n di ti o n s Parameter Temperature Range1 Power Supply Tolerance Commercial Industrial Military Units 0 to +70 5 -40 to +85 10 -55 to +125 10 C %VCC Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5V or less than GND - 0.5V, the internal protection diode will be forward biased and can draw excessive current. E l e ct r i c al S pe c i fi ca t i o n s Commercial Symbol VOH1 Parameter (IOH = -10 mA) (IOH = -6 mA) (IOH = -4 mA) VOL1 (IOL = 10 mA) (IOL = 6 mA) VIL VIH Input Transition Time tR, tF CIO I/O Capacitance2 Standby Current, ICC3 (typical = 1 mA) ICC(D) Dynamic VCC Supply Current IV Curve4 -0.3 2.0 0.5 0.33 0.8 VCC + 0.3 500 10 2.0 -0.3 2.0 0.5 0.33 0.8 VCC + 0.3 500 10 20 -0.3 2.0 0.40 0.8 VCC + 0.3 500 10 10 -0.3 2.0 0.40 0.8 VCC + 0.3 500 10 20 Min. 2.4 3.84 Max. Commercial -F Min. 2.4 3.84 3.7 3.7 Max. Min. Industrial Max. Min. Military Units Max. V V V V V V V ns pF mA See the "Power Dissipation" section on page 14. Can be converted from IBIS model on the web. Notes: 1. Only one output tested at a time. VCC = min. 2. 3. 4. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation. The IBIS model can be found at www.actel.com/support/support/support_ibis.html. 12 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 3 . 3V O p e r at i n g C o n di t i o n s A b s o l u t e Ma x i m u m R a ti n g s 1 F r e e A ir T em p e r a t u r e Ra n ge Symbol VCC VI2 VO TSTG Parameter DC Supply Voltage Input Voltage Output Voltage Storage Temperature Limits -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 Units V V V C R e c o m m e n de d O pe r at i n g C o n d i ti o n s Parameter Temperature Range1 Commercial 0 to +70 5 Units C %V Power Supply Tolerance Note: 1. Ambient temperature (TA) is used for commercial. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5V or less than GND - 0.5V, the internal protection diodes will forward bias and can draw excessive current. E l e ct r i c al S pe c i f i ca t i o n s Commercial Parameter Min. VOH1 VOL1 VIL VIH Input Transition Time tR, tF2 CIO I/O Capacitance2, 3 Standby Current, ICC4 (typical = 0.3 mA) ICC(D) Dynamic VCC Supply Current IV Curve4 (IOH = -4 mA) (IOH = -3.2 mA) (IOL = 6 mA) -0.3 2.0 2.15 2.4 0.4 0.8 VCC + 0.3 500 10 0.75 See the "Power Dissipation" section on page 14. Can be converted from IBIS model on the web. Max. V V V V V ns pF mA Units Notes: 1. Only one output tested at a time. VCC = min. 2. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 3. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. 4. The IBIS model can be found at www.actel.com/support/support/support_ibis.html. Discontinued - v3.0 13 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Th e r m a l C h a ra c t er i s ti c s Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package with still air at commercial temperature is as follows: The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Max. junction temp. (C) - Max. commercial temp. = 150C - 70C = 2.4W -----------------------------------------------------------------------------------------------------------------------------------------------------------34C/W ja (C/W) ja Package Type Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Thin Quad Flat Pack Power Quad Flat Pack Power Quad Flat Pack Very Thin Quad Flat Pack Pin Count 100 144 160 208 84 176 208 240 100 Still Air 42C/W 36C/W 34C/W 25C/W 37C/W 32C/W 16.8C/W 16.1C/W 43C/W 300 ft/min 33C/W 29C/W 27C/W 16.2C/W 28C/W 25C/W 11.4C/W 10.6C/W 35C/W Maximum Power Dissipation Still Air 1.9 W 2.2 W 2.4 W 3.2 W 2.2 W 2.5 W 4.8 W 5.0 W 1.9 W 300 ft/min 2.4 W 2.8 W 3.0 W 4.9 W 2.9 W 3.2 W 7.0 W 7.5 W 2.3 W P ow e r D i s s i p a t i on G e n e r a l P ow e r E qu a t i o n P = [ICCstandby + ICCactive] * VCC + IOL* VOL* N + IOH * (VCC - VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematic because their values depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. S t a t ic P ow e r C om p o ne nt The power dissipation due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial worst case conditions. ICC 2 mA VCC 5.25 V Power 10.5 mW The static power dissipation by TTL loads depends on the number of outputs driving HIGH or LOW and the DC load current. Again, this number is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving LOW and 140 mW with all outputs driving HIGH. The actual dissipation will average somewhere in between as I/Os switch states with time. A c t i v e P ow e r C om p o n e n t Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. 14 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s E q u iv al en t C ap a ci t an c e The power dissipated by a CMOS circuit can be expressed by Equation 1 Power (W) = CEQ * VCC2 * F where: CEQ is the equivalent capacitance expressed in picofarads (pF). VCC is power supply in volts (V). F is the switching frequency in megahertz (MHz). (1) fp fq1 fq2 = Average output buffer switching rate in MHz = Average first routed array clock rate in MHz = Average second routed array clock rate in MHz F ix ed C ap a ci t an c e V a lu es f or A c t el F P G A s (pF) Table 5. Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C E Q Val ue s f o r A ct el FP G A s Device Type A1225XL A1240XL A3265DX A1280XL A32100DX A32140DX A32200DX A32300DX r1 routed_Clk1 106 134 158 168 178 190 230 285 r2 routed_Clk2 106 134 158 168 178 190 230 285 Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) 5.2 11.6 23.8 D e t e r m i n i n g Av e r a g e S w i t c h i n g F re qu en c y Routed Array Clock Buffer Loads (CEQCR) 3.5 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = VCC2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2) where: m n p q1 = Number of logic modules switching at frequency fm = Number of input buffers switching at frequency fn = Number of output buffers switching at frequency fp = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock r1 = lFixed capacitance due to first routed array clock r2 = Fixed capacitance due to second routed array clock CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL = Output load capacitance in p fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz To determine the switching frequency for a design, the user must have a detailed understanding of the data input values to the circuit. The following guidelines represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation. Logic Modules (m) = 80% of Combinatorial Modules = # of Inputs/4 = # Outputs/4 = 40% of Sequential Modules = 40% of Sequential Modules = 35 pF = F/10 = F/5 = F/10 =F = F/2 Inputs Switching (n) Outputs Switching (p) First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Discontinued - v3.0 15 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 1 20 0 X L T i m i ng M o d el * Input Delays Internal Delays Combinatorial I/O Module Logic Module tINYL = 1.3 ns t IRD2 = 3.2 ns Predicted Routing Delays Output Delays I/O Module tDLH = 3.8 ns D Q tPD = 2.6 ns tRD1 = 0.8 ns tRD2 = 1.3 ns tRD4 = 2.0 ns tRD8 = 3.2 ns G tINH = 0.0 ns tINSU = 0.3 ns tINGL = 2.6 ns Sequential Logic Module Combinatorial Logic included in tSUD I/O Module tDLH = 3.8 ns D Q tRD1 = 0.8 ns D Q tENHZ = 5.4 ns G tOUTH = 0.0 ns tOUTSU = 0.3 ns tGLH = 4.2 ns Array Clocks tCKH = 5.7 ns FMAX = 225 MHz FO = 256 tSUD = 0.4 ns tHD = 0.0 ns tCO = 2.6 ns tLCO = 10.7 ns (64 loads, pad-pad) Notes: 1. *Values shown for A1225XL-2 at worst-case commercial conditions. 2. Input Module Predicted Routing Delay 16 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 3 20 0 D X T i m i n g M od e l ( Lo g i c F u nc t i o n s u s i n g A r r ay C l o c k s ) * Input Delays I/O Module tINPY = 1.2 ns t IRD1 = 2.7 ns Internal Delays Predicted Routing Delays Output Delays I/O Module Combinatorial Module D Q tPD = 2.1 ns tRD1 = 0.3 ns tRD2 = 0.7 ns tRD4 = 1.2 ns tDLH = 3.2 ns G tINH = 0.0 ns tINSU = 0.4 ns tINGO = 2.8 ns Decode Module tPDD = 2.1 ns I/O Module tDLH = 3.2 ns tRDD = 0.4 ns Sequential Logic Module Combinatorial Logic included in tSUD D Q tRD1 = 0.3 ns D Q tENHZ = 7.1 ns G tLH = 0.0 ns tLSU = 0.4 ns tGHL= 6.5 ns tSUD = 0.3 ns tHD = 0.0 ns Array Clocks tCKH = 5.3 ns FMAX = 173 MHz tCO = 2.0 ns *Values shown for A3265DX-2 at worst-case commercial conditions. Discontinued - v3.0 17 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 3 20 0 D X Ti m i n g M od e l ( Lo g i c F u nc t i o ns u s i n g Q ua d r an t C l o c k s )* Input Delays I/O Module tINPY = 1.4 ns t IRD1 = 1.9 ns Internal Delays Predicted Routing Delays Output Delays I/O Module Combinatorial Module D Q tPD = 2.0 ns tRD1 = 1.1 ns tRD2 = 1.7 ns tRD4 = 2.6 ns tDLH = 3.7 ns G tINH = 0.0 ns tINSU = 0.45 ns tINGO = 3.3 ns Decode Module tPDD = 2.5 ns I/O Module tDLH = 3.7 ns tRDD = 0.3 ns Sequential Logic Module Combinatorial Logic included in tSUD D Q tRD1 = 1.1 ns D Q tENHZ = 8.3 ns G tLH = 0.0 ns tLSU = 0.26 ns tGHL= 8.9 ns tSUD = 0.3 ns tHD = 0.0 ns Quadrant Clocks tCKH = 5.3 ns** FMAX = 165 MHz tCO = 2.3 ns * Preliminary values shown for A32200DX-3 at worst-case commercial conditions. ** Load-dependent. 18 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 3 20 0 D X T i m i n g M od e l ( S R A M F u n ct i o n s ) * Input Delays I/O Module tINPY = 1.4 ns t IRD1 = 1.9 ns D Q G tINSU = 0.45 ns tINH = 0.05 ns tINGO = 3.3 ns Predicted Routing Delays WD [7:0] WRAD [5:0] BLKEN WEN WCLK tADSU = 1.5 ns tADH = 0.0 ns tWENSU = 2.6 ns tBENS = 2.6 ns RD [7:0] RDAD [5:0] REN tRD1 = 1.1 ns I/O Module tDLH = 3.7 ns D Q RCLK tADSU = 1.5 ns tADH = 0.0 ns tRENSUA = 0.6 ns tRCO = 3.2 ns G tGHL= 8.9 ns tLSU = 0.26 ns tLH = 0.0 ns ARRAY CLOCKS FMAX = 165 MHz *Values shown for A32200DX-3 at worst-case commercial conditions. Discontinued - v3.0 19 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ar a m e t er M e a s u re m e n t O u t pu t B uffe r D el ay s E D TRIBUFF PAD To AC test loads (shown below) In PAD VOL 50% 50% VOH 1.5V 1.5V E PAD 50% VCC 50% 1.5V VOL 10% tENLZ E PAD GND 50% 50% VOH 1.5V 90% tENHZ tDLH tDHL tENZL tENZH A C Tes t L o a d s Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 35 pF To the output under test R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k3/4 35 pF I n pu t B uff e r D e lay s M od u l e D e l a y s PAD INBUF Y S A B Y S, A or B 3V PAD Y GND tINYH 1.5V 1.5V VCC 50% tINYL 0V 50% Y 50% 50% 50% tPLH tPHL 50% tPLH 50% Y 50% tPHL 20 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s S e qu e n ti a l M o d u l e T i m i n g C h a ra c t er i s t i c s Fl ip -F lo ps a n d La tc he s D E CLK PRE CLR Y (Positive Edge Triggered) tHD D1 tSUD G, CLK tSUENA tHENA E tCO Q tRS PRE, CLR tWASYN Note: D represents all data functions involving A, B, and S for multiplexed flip-flops. tWCLKI tWCLKA tA Discontinued - v3.0 21 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s S eq u e n ti a l T i m i n g C h ar a c te r i s t i c s (continued) I n pu t B uf f e r L at c h es DATA PAD G IBDL CLK PAD CLKBUF DATA tINH G tINSU tHEXT CLK tSUEXT O u t pu t B uf f e r L at c h es D OBDLHS G PAD D tOUTSU G tOUTH 22 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s D e c od e M o d ul e T i m i n g A B C D E F G Y H VCC A-G, H 50% VCC Y tPHL tPLH S R A M T i m i n g C h ar a ct e r i s t i c s Write Port WRAD [5:0] BLKEN WEN WCLK WD [7:0] RAM Array 32x8 or 64x4 (256 Bits) Read Port RDAD [5:0] LEW REN RCLK RD [7:0] Discontinued - v3.0 23 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s D u a l - P o rt S R A M Ti m i n g W a v e fo r m s 32 0 0D X S R A M Wr i t e O pe r a t io n tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU WEN tBENSU BLKEN Valid tBENH tWENH tADH tRCKHL Note: Identical timing for falling-edge clock. 3200DX SRAM Synchronous Read Operation tCKHL RCLK tRCKHL tRENSU REN tADSU RDAD[5:0] Valid tRENH tADH tRCO tDOH RD[7:0] Old Data New Data Note: Identical timing for falling-edge clock. 24 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 32 0 0D X S R A M A s y nc h ro n ou s R e a d O pe r a t io n-- Typ e 1 (Read Address Controlled) tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data 1 ADDR2 tRPD Data 2 32 0 0D X S R A M A s y nc h ro n ou s R e a d O pe r a t io n-- Typ e 2 (Write Address Controlled) WEN tWENSU tWENH WD[7:0] WRAD[5:0] BLKEN Valid tADSU tADH tRPD tDOH WCLK RD[7:0] Old Data New Data Discontinued - v3.0 25 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P re d i c ta b l e P e rf o rm an c e : T i g ht D e l a y D i s tr i b u ti o n s Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increase. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The Integrator Series delivers a very tight fanout delay distribution. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented PLICE antifuse offers a very low resistive/capacitive interconnect. The antifuses, fabricated in 0.6 micron lithography, offer nominal levels of 100 ohms resistance and 7.0 femtofarad (fF) capacitance per antifuse. The Integrator Series fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. T i m i n g C h a ra c t er i s ti c s are not determined until after placement and routing of the user's design is complete. Delay values may then be determined by using the Designer Series utility or performing simulation with post-layout delays. C r i t ic al N e t s a nd Typ ic a l N et s Propagation delays in this data sheet apply to typical nets, which are used for initial design performance evaluation. The abundant routing resources in the Integrator Series architecture allows for deterministic timing. Using DirectTime, a timing-driven place and route tool in Actel's Designer Series development software, the designer may specify timing-critical nets and system clock frequency. Using these timing specifications, the place and route software optimize the design layout to meet the user's specifications. L on g Tr a c ks Some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximately 3 ns to 6 ns delay, which is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating Timing characteristics for devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all Integrator Series members. Internal routing delays are device-dependent. Design dependency means actual delays A timing derating factor of 0.45 is used to reflect best-case processing. Note that this factor is relative to the "standard speed" timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. T i m i n g D e r at i n g F ac t o r ( T e m p er a tu r e an d V o l t a ge ) Industrial Min. (Commercial Specification) x 0.69 Max. 1.11 Min. 0.67 Military Max. 1.23 T i m i n g D e r at i n g F ac t o r f o r D es ig n s a t T y p i c al T em p er a tu r e (T J = 2 5 C ) a nd V ol t a g e ( 5 . 0 V ) (Maximum Specification, Worst-Case Condition) x 0.85 Note: This derating factor applies to all routing and propagation delays. 26 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s T e m p er a tu r e an d V o l t a ge D er a ti ng F a c to r s (N or m a l i z ed t o W o r s t - C a s e C o m m e r c i a l , T J = 4 . 7 5 V , 7 0 C ) -55 4.50 4.75 5.00 5.25 5.50 0.75 0.71 0.69 0.68 0.67 -40 0.79 0.75 0.72 0.69 0.69 0 0.86 0.82 0.80 0.77 0.76 25 0.92 0.87 0.85 0.82 0.81 70 1.06 1.00 0.97 0.95 0.93 85 1.11 1.05 1.02 0.98 0.97 125 1.23 1.16 1.13 1.09 1.08 Junction Temperature and Voltage Derating Curves (Normalized to Worst-Case Commercial, TJ = 4.75V, 70C) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 4.50 Note: Derating Factor 125C 85C 70C 25C 0C -40C -55C 4.75 5.00 5.25 5.50 Voltage (V) This derating factor applies to all routing and propagation delays. Discontinued - v3.0 27 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 25 X L T i m i n g C h ar a ct e r i s t i c s ( Wo r s t -C as e C o m m erci al C o n di t io ns , V C C = 4 .7 5 V, T J = 7 0 C ) `-3' Speed Parameter Description 1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Min. Max. Logic ModulePropagation Delays tPD1 tCO tGO tRS Single Module 2.6 2.6 2.6 2.6 3.0 3.0 3.0 3.0 3.5 3.5 3.5 3.5 5.0 5.0 5.0 5.0 4.2 4.2 4.2 4.2 ns ns ns ns Sequential Clk-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 2 Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3,4 0.8 1.3 1.7 2.0 3.2 0.9 1.4 1.8 2.3 3.5 1.1 1.7 2.2 2.7 4.2 1.57 2.43 3.15 3.86 6.00 1.3 2.0 2.6 3.2 5.0 ns ns ns ns ns Sequential Timing Characteristics Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.4 0.0 0.8 0.0 3.2 3.2 6.5 0.0 0.3 0.0 0.3 225 0.4 0.0 0.9 0.0 3.6 3.6 7.4 0.0 0.4 0.0 0.4 200 0.5 0.0 1.0 0.0 4.3 4.3 8.7 0.0 0.4 0.0 0.4 170 0.7 0.0 1.4 0.0 6.1 6.1 12.4 0.0 0.6 0.0 0.6 120 0.6 0.0 1.2 0.0 5.2 5.2 10.4 0.0 0.5 0.0 0.5 115 ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time. 5. VCC = 3.0V for 3.3V specifications. 28 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 25 X L T i m i n g C h ar a ct e r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y High Pad-to-Y Low G-to-Y High G-to-Y Low 1 1.1 1.3 2.0 2.6 1.2 1.4 2.3 3.0 1.4 1.7 2.7 3.5 2.0 2.4 3.9 5.0 1.7 2.0 3.2 4.2 ns ns ns ns Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.9 3.2 3.8 4.1 5.2 3.3 3.6 4.2 4.6 5.9 3.9 4.3 5.0 5.4 6.9 5.6 6.1 7.2 7.7 9.9 4.7 5.2 6.0 6.5 8.3 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 2.6 3.2 5.4 5.6 225 200 2.6 2.7 2.6 2.7 0.8 0.8 0.0 0.0 2.9 3.7 6.1 6.3 200 180 5.1 5.7 5.0 5.7 3.0 3.1 3.0 3.1 0.9 0.9 0.0 0.0 3.4 4.3 7.2 7.4 170 155 5.8 6.5 5.7 6.5 3.5 3.6 3.5 3.6 1.0 1.0 0.0 0.0 4.9 6.1 10.3 10.6 120. 105 6.8 7.6 6.7 7.6 5.0 5.1 5.0 5.1 1.4 1.4 0.0 0.0 4.1 5.2 8.6 8.9 115 105 9.7 10.9 9.6 10.9 4.2 4.3 4.2 4.3 1.2 1.2 8.2 9.1 8.0 9.1 ns ns ns ns ns ns ns ns MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Discontinued - v3.0 29 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 25 X L T i m i n g C h ar a ct e r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description 1 `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std" Speed Min. Max. Units Min. Max. TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, Low to High Capacitive Loading, High to Low 1 3.8 4.1 3.8 4.1 5.4 5.4 4.2 4.7 9.0 12.8 0.04 0.05 4.3 4.6 4.3 4.7 6.1 6.1 4.8 5.4 10.0 14.4 0.04 0.06 5.0 5.4 5.0 5.5 7.2 7.2 5.6 6.3 12.0 17.0 0.05 0.07 7.1 7.7 7.1 7.9 10.3 10.3 8.0 9.0 17.2 24.3 0.06 0.08 6.0 6.5 6.0 6.5 8.6 8.6 6.7 7.6 14.4 20.4 0.06 0.08 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, Low to High Capacitive Loading, High to Low 4.8 3.4 3.8 4.1 5.4 5.4 4.2 4.7 10.7 15.0 0.05 0.05 5.4 3.8 4.3 4.7 6.1 6.1 4.8 5.4 11.8 17.0 0.06 0.05 6.4 4.5 5.0 5.5 7.2 7.2 5.6 6.3 14.2 20.0 0.07 0.06 9.1 6.4 7.1 7.9 10.3 10.3 8.0 9.0 20.3 28.6 0.08 0.07 7.7 5.4 6.0 6.6 8.6 8.6 6.7 7.6 17.0 24.0 0.08 0.07 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF Note: 1. Delays based on 35 pF loading. 30 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 40 X L T i m i n g C h ar a ct e r i s t i c s ( Wo r s t -C as e C o m m erci al C o n di t io ns , V C C = 4 .7 5 V, T J = 7 0 C ) `-3' Speed Parameter Description 1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Min. Max. Logic ModulePropagation Delays tPD1 tCO tGO tRS Single Module 2.6 2.6 2.6 2.6 3.0 3.0 3.0 3.0 3.5 3.5 3.5 3.5 5.0 5.0 5.0 5.0 4.2 4.2 4.2 4.2 ns ns ns ns Sequential Clk-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 2 Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3, 4 1.1 1.3 1.7 2.3 3.4 1.2 1.4 1.9 2.6 3.8 1.4 1.7 2.2 3.0 4.5 2.0 2.4 3.1 4.3 6.4 1.7 2.0 2.6 3.6 5.4 ns ns ns ns ns Sequential Timing Characteristics tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.4 0.0 0.8 0.0 3.4 3.4 6.8 0.0 0.3 0.0 0.3 215 0.4 0.0 0.9 0.0 3.8 3.8 7.7 0.0 0.4 0.0 0.4 190 0.5 0.0 1.0 0.0 4.5 4.5 9.1 0.0 0.4 0.0 0.4 160 0.7 0.0 1.4 0.0 6.4 6.4 13.0 0.0 0.6 0.0 0.6 110 0.6 0.0 1.2 0.0 5.4 5.4 10.9 0.0 0.5 0.0 0.5 105 ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time. 5. VCC = 3.0V for 3.3V specifications. Discontinued - v3.0 31 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 40 X L T i m i n g C h ar a ct e r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y High Pad-to-Y Low G-to-Y High G-to-Y Low 1 1.1 1.3 2.0 2.6 1.2 1.4 2.3 3.0 1.4 1.7 2.7 3.5 2.0 2.4 3.9 5.0 1.7 2.0 3.2 4.2 ns ns ns ns Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.9 3.4 3.8 4.1 5.6 3.3 3.8 4.3 4.7 6.3 3.9 4.5 5.1 5.5 7.4 5.6 6.4 7.3 7.9 10.6 4.7 5.4 6.1 6.6 8.9 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 2.6 3.2 5.6 6.0 215 195 2.7 2.9 2.7 2.9 0.8 0.8 0.0 0.0 2.9 3.7 6.3 6.8 190 170 5.1 5.7 5.0 5.7 3.1 3.3 3.1 3.3 0.9 0.9 0.0 0.0 3.4 4.3 7.4 8.0 160 144 5.8 6.5 5.7 6.5 3.6 3.9 3.6 3.9 1.0 1.0 0.0 0.0 4.9 6.1 10.6 11.4 110 100 6.8 7.6 6.7 7.6 5.1 5.6 5.1 5.6 1.4 1.4 0.0 0.0 4.1 5.2 8.9 9.6 105 95 9.7 10.9 9.6 10.9 4.3 4.7 4.3 4.7 1.2 1.2 8.2 9.1 8.0 9.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 32 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 40 X L T i m i n g C h ar a ct e r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description 1 `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, Low to High Capacity Loading, High to Low 3.8 4.1 3.8 4.1 5.4 5.4 4.2 4.7 9.2 12.9 0.04 0.05 4.3 4.6 4.3 4.7 6.1 6.1 4.8 5.4 10.5 14.6 0.04 0.06 5.0 5.4 5.0 5.5 7.2 7.2 5.6 6.3 12.3 17.2 0.05 0.07 7.1 7.7 7.1 7.9 10.3 10.3 8.0 9.0 17.6 24.6 0.06 0.08 6.0 6.5 6.0 6.6 8.6 8.6 6.7 7.6 14.8 20.6 0.06 0.08 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, Low to High Capacity Loading, High to Low 4.8 3.4 3.8 4.1 5.4 5.4 4.2 4.7 10.9 15.2 0.05 0.05 5.4 3.8 4.3 4.7 6.1 6.1 4.8 5.4 12.4 17.2 0.06 0.05 6.4 4.5 5.0 5.5 7.2 7.2 5.6 6.3 14.5 20.3 0.07 0.06 9.1 6.4 7.1 7.9 10.3 10.3 8.0 9.0 20.7 29.0 0.08 0.07 7.7 5.4 6.0 6.6 8.6 8.6 6.7 7.6 17.4 24.4 0.08 0.07 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF Note: 1. Delays based on 35 pF loading. Discontinued - v3.0 33 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 65 D X T i m i n g C h a ra c t er i s ti c s (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Logic ModulePropagation Delays1 Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay 2 2.1 2.5 2.4 2.8 2.9 3.4 3.7 4.4 3.2 3.7 ns ns Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 0.3 0.7 1.0 1.4 2.7 0.46 0.4 0.8 1.2 1.6 3.2 0.5 0.5 0.9 1.4 1.9 3.7 0.62 0.6 1.2 1.8 2.4 4.9 0.8 0.5 1.0 1.6 2.1 4.1 0.7 ns ns ns ns ns ns Sequential Timing Characteristics3, 4 Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.75 0.0 3.7 4.9 0.35 0.0 2.3 0.9 0.0 4.2 5.5 2.3 2.1 0.4 0.0 2.7 1.0 0.0 4.9 6.5 2.7 2.4 0.47 0.0 3.1 1.3 0.0 6.4 8.4 3.1 2.9 0.6 0.0 4.1 1.1 0.0 5.5 7.1 4.1 3.7 0.5 0.0 3.5 3.5 3.2 ns ns ns ns ns ns ns ns ns Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time. 5. VCC = 3.0V for 3.3V specifications. 34 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 65 D X T i m i n g C h a ra c t er i s ti c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.5 5.1 1.4 3.3 0.0 0.6 5.9 1.6 3.7 0.0 0.7 6.9 1.9 4.4 0.0 0.9 9.0 2.4 5.7 0.0 0.8 7.7 2.1 4.8 ns ns ns ns ns Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD5 tIRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 3.2 3.6 3.9 4.5 6.6 0.37 3.7 4.2 4.5 5.2 7.5 0.4 4.3 4.9 5.3 6.1 8.8 0.5 5.6 6.4 6.9 7.9 11.4 0.7 4.8 5.4 5.9 6.7 9.7 0.6 ns ns ns ns ns ns Global Clock Network tCKH tCKL tPW tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width Maximum Skew FO=32 FO=256 FO=32 FO=256 FO=32 FO=256 FO=32 FO=256 FO=32 FO=256 FO=32 FO=256 FO=32 FO=256 FO=32 FO=256 0.0 0.0 2.5 2.5 5.0 6.0 173 151 3.2 3.4 0.75 0.75 0.0 0.0 2.9 2.9 7.2 8.3 138 121 6.3 7.4 5.9 6.4 3.7 3.9 0.9 0.9 0.0 0.0 3.4 3.4 8.3 9.5 120 105 7.1 8.4 6.6 7.3 4.3 4.6 1.0 1.0 0.0 0.0 4.4 4.4 11.9 13.6 84 74 8.4 9.9 7.8 8.6 5.6 6.0 1.3 1.3 0.0 0.0 3.8 3.8 9.2 10.6 108 95 10.9 12.8 10.1 11.2 4.8 5.1 1.1 1.1 9.2 10.9 8.6 9.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Discontinued - v3.0 35 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 65 D X T i m i n g C h a ra c t er i s ti c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description 1 `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTLL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad)32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output Timing1 0.5 0.0 3.8 4.6 4.8 5.2 8.3 8.3 8.3 7.7 0.6 0.0 9.8 13.9 0.037 0.05 0.3 4.3 5.2 5.4 5.9 9.5 9.5 9.4 8.7 0.7 0.0 11.1 15.7 0.04 0.03 0.4 5.0 6.1 6.4 6.9 11.1 11.1 11.1 10.2 0.9 0.0 13.1 18.5 0.05 0.07 0.5 6.5 7.9 8.3 9.0 14.5 14.5 14.4 13.3 0.8 0.0 17.0 24.1 0.071 0.1 0.7 5.5 6.7 7.1 7.6 12.3 12.3 12.3 11.3 ns ns ns ns ns ns ns ns ns ns 14.5 20.5 0.06 0.08 0.6 ns ns ns/pF ns/pF ns/pF CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTLL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output 0.5 0.0 4.6 3.8 4.8 5.2 8.3 8.3 8.3 9.0 0.6 0.0 11.7 16.4 0.05 0.04 0.3 5.2 4.3 5.5 5.9 9.5 9.5 9.4 10.2 0.7 0.0 13.3 18.5 0.06 0.05 0.4 6.1 5.0 6.4 6.9 11.1 11.1 11.1 12.0 0.9 0.0 15.6 21.8 0.07 0.06 0.5 7.9 6.5 8.4 9.0 14.5 14.5 14.4 15.6 0.8 0.0 20.3 28.3 0.1 0.1 0.7 6.7 5.5 7.1 7.6 12.3 12.3 12.3 13.3 ns ns ns ns ns ns ns ns ns ns 17.3 24.1 0.1 0.1 0.6 ns ns ns/pF ns/pF ns/pF Note: 1. Delays based on 35pF loading. 36 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 80 X L T i m i n g C h ar a ct e r i s t i c s ( Wo r s t -C as e C o m m erci al C o n di t io ns , V C C = 4 .7 5 V, T J = 7 0 C ) `-3' Speed Parameter Description 1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Min. Max. Logic ModulePropagation Delays tPD1 tCO tGO tRS Single Module 2.6 2.6 2.6 2.6 3.0 3.0 3.0 3.0 3.5 3.5 3.5 3.5 5.0 5.0 5.0 5.0 4.2 4.2 4.2 4.2 ns ns ns ns Sequential Clk-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 2 Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3,4 1.3 1.8 2.2 2.6 5.0 1.4 2.0 2.5 3.0 5.7 1.7 2.4 2.9 3.5 6.7 2.4 3.4 4.1 5.0 9.6 2.0 2.9 3.5 4.2 8.0 ns ns ns ns ns Sequential Timing Characteristics tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.4 0.0 0.8 0.0 3.7 3.7 8.0 0.0 0.3 0.0 0.3 200 0.4 0.0 0.9 0.0 4.3 4.3 8.7 0.0 0.4 0.0 0.4 167 0.5 0.0 1.0 0.0 4.9 4.9 10.0 0.0 0.4 0.0 0.4 130 0.7 0.0 1.4 0.0 7.0 7.0 14.0 0.0 0.6 0.0 0.6 90 0.6 0.0 1.2 0.0 5.9 5.9 12.0 0.0 0.5 0.0 0.5 110 ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time. 5. VCC = 3.0V for 3.3V specifications. Discontinued - v3.0 37 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 80 X L T i m i n g C h ar a ct e r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y High Pad-to-Y Low G-to-Y High G-to-Y Low 1 1.1 1.3 2.0 2.6 1.2 1.4 2.3 3.0 1.4 1.7 2.7 3.5 2.0 2.4 3.9 5.0 1.7 2.0 3.2 4.2 ns ns ns ns Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.2 3.7 4.0 4.6 6.6 3.7 4.2 4.5 5.2 7.5 4.3 4.9 5.3 6.1 8.8 6.1 7.0 7.6 8.7 12.6 5.2 5.9 6.4 7.3 10.6 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 2.6 3.2 6.5 7.2 200 180 3.2 3.5 3.2 3.5 0.8 0.8 0.0 0.0 2.9 3.7 7.4 8.0 167 150 5.1 5.7 5.0 5.7 3.5 3.9 3.5 3.9 0.9 0.9 0.0 0.0 3.4 4.3 8.7 9.6 143 130 5.8 6.5 5.7 6.5 4.3 4.6 4.3 4.6 1.0 1.0 0.0 0.0 4.9 6.1 12.4 13.7 100 90 6.8 7.6 6.7 7.6 6.1 6.6 6.1 6.6 1.4 1.4 0.0 0.0 4.1 5.2 10.4 11.5 120 110 9.7 10.9 9.6 10.9 5.2 5.5 5.2 5.5 1.2 1.2 8.2 9.1 8.0 9.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 38 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 1 2 80 X L T i m i n g C h ar a ct e r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, Low to High Capacitive Loading, High to Low 1 3.8 4.1 3.8 4.1 5.4 5.4 4.2 4.7 9.8 13.9 0.04 0.05 4.3 4.6 4.3 4.7 6.1 6.1 4.8 5.4 11.0 15.7 0.04 0.06 5.0 5.4 5.0 5.5 7.2 7.2 5.6 6.3 13.1 18.5 0.05 0.07 7.1 7.7 7.1 7.7 10.3 10.3 8.0 9.0 18.7 26.4 0.06 0.08 6.0 6.5 6.0 6.6 8.6 8.6 6.7 7.6 15.7 22.2 0.06 0.08 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, Low to High Capacitive Loading, High to Low 4.8 3.4 3.8 4.1 5.4 5.4 4.2 4.7 11.6 16.4 0.05 0.05 5.4 3.8 4.3 4.7 6.1 6.1 4.8 5.4 13.0 18.5 0.06 0.05 6.4 4.5 5.0 5.5 7.2 7.2 5.6 6.3 15.5 21.8 0.07 0.06 9.1 6.4 7.1 7.9 10.3 10.3 8.0 9.0 22.2 31.2 0.08 0.07 7.7 5.4 6.0 6.6 8.6 8.6 6.7 7.6 18.6 26.2 0.08 0.07 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF Note: 1. Delays based on 35 pF loading. Discontinued - v3.0 39 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 10 0 D X T i m i n g C h a ra c te r i s t i c s (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3 Speed Parameter Description Min. Max. `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Logic ModulePropagation Delays Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay 2.2 2.4 2.6 2.7 3.0 3.1 3.5 3.7 5.2 5.7 4.1 4.3 ns ns Predicted Module Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 1.0 1.4 1.8 2.4 4.2 0.3 1.1 1.7 2.1 2.7 5.0 0.37 1.3 1.9 2.5 3.1 5.6 0.4 1.5 2.2 2.9 3.7 6.6 0.5 3.3 4.3 5.2 6.5 10.0 0.4 1.7 2.5 3.4 4.3 7.7 0.6 ns ns ns ns ns ns Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.6 0.0 3.1 4.1 0.3 0.0 2.2 0.75 0.0 3.7 4.8 2.2 2.2 0.37 0.0 2.6 0.9 0.0 4.2 5.4 2.6 2.6 0.4 0.0 3.0 1.0 0.0 4.9 6.4 3.0 3.0 0.5 0.0 3.5 1.4 0.0 7.0 7.0 3.5 3.5 0.7 0.0 5.0 0.85 0.0 5.7 7.5 5.0 5.0 0.6 0.0 4.1 4.1 4.1 ns ns ns ns ns ns ns ns ns 40 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 10 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3 Speed Parameter Description Min. Max. `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Logic Module Timing Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 6.4 6.4 3.2 3.2 1.5 0.0 0.6 3.2 2.6 0.0 2.6 0.0 7.5 7.5 3.8 3.8 1.8 0.0 0.7 3.8 3.0 0.0 3.1 0.0 8.5 8.5 4.3 4.3 2.0 0.0 0.8 4.3 3.4 0.0 3.5 0.0 10.0 10.0 5.0 5.0 2.4 0.0 0.9 5.0 4.0 0.0 4.1 0.0 14.3 14.3 7.1 7.1 3.4 0.0 1.3 7.1 5.7 0.0 5.8 0.0 11.7 11.7 5.9 5.9 2.8 0.0 1.0 5.9 4.7 0.0 4.8 0.0 ns ns ns ns ns ns ns ns ns ns ns ns Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 8.3 1.5 0.0 0.57 3.2 2.6 0.0 1.1 7.7 9.8 1.8 0.0 0.7 3.8 3.0 0.0 1.35 9.0 11.1 2.0 0.0 0.8 4.3 3.4 0.0 1.5 10.2 13.0 2.4 0.0 0.9 5.0 4.0 0.0 1.8 12.0 18.6 3.4 0.0 1.3 7.1 5.7 0.0 2.6 17.2 15.2 2.8 0.0 1.0 5.9 4.7 0.0 2.1 14.1 ns ns ns ns ns ns ns ns ns Discontinued - v3.0 41 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 10 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output1 Input Latch Hold1 0.0 0.45 4.4 1.4 2.9 0.0 0.5 4.8 1.65 3.4 0.0 0.6 5.9 1.9 3.8 0.0 0.7 6.9 2.2 4.5 0.0 1.0 9.8 3.1 6.4 0.0 0.82 8.1 2.5 5.3 ns ns ns ns ns Input Latch Set-Up1 Latch Active Pulse Width1 Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.6 2.0 2.6 2.6 4.1 1.75 2.4 3.0 3.0 4.8 2.1 2.7 3.4 3.4 5.4 2.5 3.2 4.0 4.0 6.4 3.6 4.6 5.7 5.7 9.1 2.9 3.8 4.7 4.7 7.5 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 2.2 2.7 5.0 5.5 183 167 2.5 2.7 2.5 2.7 0.6 0.6 0.0 0.0 2.5 3.2 6.0 6.4 159 145 4.7 5.7 4.8 6.4 2.9 3.2 2.9 3.2 0.75 0.75 0.0 0.0 2.9 3.7 7.4 8.2 146 133 5.6 6.75 5.6 7.5 3.3 3.7 3.3 3.7 0.9 0.9 0.0 0.0 3.4 4.3 7.9 8.6 127 116 6.3 7.7 6.4 8.5 3.9 4.3 3.9 4.3 1.0 1.0 0.0 0.0 4.9 6.1 12.4 13.7 89 81 7.4 9.0 7.5 10.0 5.6 6.1 5.5 6.1 1.4 1.4 0.0 0.0 4.0 6.1 9.3 10.1 108 99 10.5 12.8 10.7 14.2 4.5 5.0 4.5 5.0 1.8 1.8 8.7 10.5 8.8 11.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 42 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 10 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description 1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output 1 3.7 4.5 4.8 5.1 8.3 8.3 8.3 9.0 0.26 0.0 8.4 11.8 0.03 0.04 0.04 0.3 0.0 4.3 5.3 5.6 6.0 9.8 9.8 9.8 10.5 0.34 0.0 9.8 13.8 0.037 0.05 0.045 4.9 6.0 6.4 6.8 11.1 11.1 11.1 12.0 0.4 0.0 11.1 15.7 0.04 0.06 0.05 5.8 7.1 7.5 8.0 13.0 13.0 13.0 14.1 0.6 0.0 13.1 18.5 0.05 0.07 0.06 8.2 10.1 10.7 11.4 18.5 18.5 18.5 20.1 0.6 0.0 18.7 26.5 0.07 0.10 0.09 6.8 8.3 8.8 9.4 15.2 15.2 15.2 16.4 ns ns ns ns ns ns ns ns ns ns 15.3 21.7 0.06 0.08 0.07 ns ns ns/pF ns/pF ns CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output 0.26 0.0 4.5 3.7 4.8 5.1 8.3 8.3 8.3 9.0 0.3 0.0 9.9 13.9 0.04 0.04 0.04 5.3 4.3 5.6 6.0 9.8 9.8 9.8 10.5 0.3 0.0 11.0 16.4 0.052 0.045 0.045 6.0 4.9 6.4 6.8 11.1 11.1 11.1 12.0 0.4 0.0 13.2 18.5 0.05 0.05 0.05 7.1 5.8 7.5 8.0 13.0 13.0 13.0 14.1 0.6 0.0 15.5 21.8 0.07 0.06 0.06 10.1 8.2 10.7 11.4 18.5 18.5 18.5 20.0 0.6 0.0 22.3 30.0 0.10 0.09 0.09 8.3 6.8 8.8 9.4 15.2 15.2 15.2 16.4 ns ns ns ns ns ns ns ns ns ns 18.2 25.6 0.08 0.07 0.07 ns ns ns/pF ns/pF ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Discontinued - v3.0 43 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 14 0 D X T i m i n g C h a ra c te r i s t i c s (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2 Speed Parameter Description 1 `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. Logic Module Propagation Delays Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay 1.8 1.9 2.3 2.5 2.8 3.0 3.6 3.8 3.2 3.5 ns ns Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 3, 4 1.0 1.4 1.8 2.2 3.8 0.5 1.3 1.9 2.4 2.9 5.0 0.7 1.6 2.2 2.8 3.4 5.9 0.78 2.0 2.8 3.7 4.5 7.7 1.0 1.8 2.5 3.3 4.0 7.0 0.91 ns ns ns ns ns ns Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.6 0.0 2.6 4.1 0.3 0.0 2.1 1.8 0.4 0.0 2.1 0.9 0.0 3.5 5.5 2.8 2.3 0.47 0.0 2.8 1.0 0.0 4.1 6.5 3.3 2.8 0.6 0.0 3.3 1.3 0.0 5.4 8.4 4.3 3.6 0.55 0.0 4.3 1.17 0.0 4.82 7.6 3.9 3.2 ns ns ns ns 3.9 ns ns ns ns ns Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time. 44 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 14 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.3 3.1 1.2 2.3 0.0 0.4 4.2 1.6 3.1 0.0 0.47 4.9 1.9 3.7 0.0 0.6 6.4 2.4 4.7 0.0 0.55 5.7 2.2 4.3 ns ns ns ns ns Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD5 tIRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 2.7 3.1 3.4 3.9 5.6 0.3 3.7 4.2 4.5 5.2 7.5 0.4 4.3 4.9 5.3 6.1 8.8 0.5 5.6 6.4 6.9 7.9 11.4 0.7 5.0 5.7 6.2 7.1 10.3 0.6 ns ns ns ns ns ns Global Clock Network tCKH tCKL tPW tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width Maximum Skew FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.0 0.0 2.2 2.2 5.7 6.6 173 151 2.7 2.9 0.6 0.6 0.0 0.0 2.9 2.9 7.6 8.3 138 121 6.2 6.8 6.12 6.7 3.7 3.9 0.9 0.9 0.0 0.0 3.4 3.4 8.3 9.5 120 105 8.3 9.1 8.2 8.9 4.3 4.6 1.0 1.0 0.0 0.0 4.4 4.4 11.9 13.6 84 74 9.7 10.7 9.6 10.5 5.6 6.0 1.3 1.3 0.0 0.0 4.0 4.0 9.0 11.1 102 90 12.7 13.9 12.5 13.6 5.0 5.41 1.17 1.17 11.4 12.5 11.3 12.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Discontinued - v3.0 45 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 14 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-2 Speed Parameter Description TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO 1 `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output Timing1 0.4 0.0 3.3 3.5 4.1 4.4 7.1 7.1 6.5 6.5 0.6 0.0 8.4 11.8 0.03 0.02 0.03 4.4 4.6 5.5 5.9 9.5 9.5 8.7 8.7 0.7 0.0 11.1 15.7 0.04 0.03 0.04 5.1 5.4 6.4 6.9 11.1 11.1 10.2 10.2 0.9 0.0 13.1 18.5 0.05 0.07 0.05 6.7 7.1 8.4 9.0 14.5 14.5 13.3 13.3 0.82 0.0 17.0 24.1 0.07 0.1 0.07 6.0 6.3 7.5 8.1 13.0 13.0 12.0 12.0 ns ns ns ns ns ns ns ns ns ns 15.4 21.7 0.06 0.08 0.06 ns ns ns/pF ns/pF ns/pF CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output 0.4 0.0 3.5 3.3 4.1 4.4 7.1 7.1 6.5 6.5 0.6 0.0 9.9 13.9 0.04 0.04 0.3 4.6 4.4 5.5 5.9 9.5 9.5 8.7 8.7 0.7 0.0 13.3 18.5 0.06 0.05 0.4 5.4 5.1 6.4 6.9 11.1 11.1 10.2 10.2 0.9 0.0 15.6 21.8 0.07 0.06 0.5 7.1 6.7 8.4 9.0 14.5 14.5 13.3 13.3 0.82 0.0 20.3 28.3 0.1 0.1 0.7 6.0 6.3 7.5 8.1 13.0 13.0 12.0 12.0 ns ns ns ns ns ns ns ns ns ns 18.3 25.6 0.08 0.07 0.6 ns ns ns/pF ns/pF ns/pF Note: 1. Delays based on 35 pF loading. 46 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 20 0 D X T i m i n g C h a ra c te r i s t i c s (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3 Speed Parameter Description Min. Max. `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Logic Module Propagation Delays Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay 2.0 2.5 2.4 2.9 2.7 3.3 3.2 3.9 4.5 5.6 3.7 4.5 ns ns Predicted Module Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 1.1 1.7 2.1 2.6 4.5 0.6 1.35 2.0 2.4 3.0 5.3 0.67 1.5 2.2 2.8 3.4 6.0 0.8 1.8 2.6 3.3 4.0 7.0 0.9 2.6 3.7 4.7 5.7 10.0 1.3 2.1 3.0 3.8 4.7 8.2 1.0 ns ns ns ns ns ns Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.6 0.0 3.1 4.1 0.3 0.0 2.3 0.75 0.0 3.7 4.9 2.3 2.0 0.35 0.0 2.7 0.9 0.0 4.2 5.5 2.7 2.4 0.4 0.0 3.1 1.0 0.0 4.9 6.5 3.1 2.7 0.47 0.0 3.6 1.4 0.0 7.0 9.2 3.6 3.2 0.7 0.0 5.1 1.17 0.0 5.7 7.6 5.1 4.5 0.55 0.0 4.2 4.2 3.7 ns ns ns ns ns ns ns ns ns Discontinued - v3.0 47 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 20 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3 Speed Parameter Description Min. Max. `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Logic Module Timing Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSU tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 6.4 6.4 3.2 3.2 1.5 0.0 0.6 3.2 2.6 0.0 2.6 0.0 7.5 7.5 3.9 3.8 1.8 0.0 0.7 3.8 3.0 0.0 3.1 0.0 8.5 8.5 4.3 4.3 2.0 0.0 0.8 4.3 3.4 0.0 3.5 0.0 10.0 10.0 5.0 5.0 2.4 0.0 0.9 5.0 4.0 0.0 4.1 0.0 14.3 14.3 7.1 7.1 3.4 0.0 1.4 7.0 5.4 0.0 5.6 0.0 11.7 11.7 5.8 5.8 2.8 0.0 1.0 5.8 4.7 0.0 4.8 0.0 ns ns ns ns ns ns ns ns ns ns ns ns Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 8.3 1.5 0.0 0.57 3.2 2.6 0.0 1.1 7.7 9.75 1.8 0.0 0.7 3.8 3.0 0.0 1.3 9.0 11.1 2.0 0.0 0.8 4.3 3.4 0.0 1.5 10.2 13.0 2.4 0.0 0.9 5.0 4.0 0.0 1.8 12.0 18.6 3.4 0.0 1.4 7.1 5.4 0.0 2.6 17.2 15.2 2.8 0.0 1.0 5.8 4.7 0.0 2.1 14.1 ns ns ns ns ns ns ns ns ns 48 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 20 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output1 Input Latch Hold1 0.0 0.45 1 1.4 3.3 0.0 0.52 5.2 1.65 3.2 0.0 0.6 5.9 1.9 4.3 0.0 0.7 6.9 2.2 5.1 0.0 1.0 9.8 2.9 7.3 0.0 0.8 8.1 2.5 6.0 ns ns ns ns ns Input Latch Set-Up1 Latch Active Pulse Width 4.4 Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD5 tIRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Delay 1.9 2.5 3.3 3.9 5.0 0.3 2.2 2.9 3.9 4.5 6.0 0.37 2.6 3.3 4.4 5.2 6.7 0.4 3.0 3.9 5.2 6.1 7.9 0.5 4.2 5.5 7.6 8.7 11.2 0.7 3.5 4.5 6.1 7.1 9.3 0.6 ns ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input Low to High Input High to Low FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 2.2 2.7 5.5 6.1 165 151 2.7 2.9 2.7 2.9 0.6 0.6 0.0 0.0 2.6 3.2 6.5 7.2 153. 140 5.3 6.1 5.2 6.8 3.2 3.45 3.2 3.45 0.75 0.75 0.0 0.0 2.9 3.7 7.4 8.2 132 121 6.2 7.2 6.2 8.0 3.7 3.9 3.7 3.9 0.9 0.9 0.0 0.0 3.4 4.3 8.7 9.6 115 105 7.1 8.2 7.0 9.0 4.3 4.6 4.3 4.6 1.0 1.0 0.0 0.0 4.9 6.1 12.4 13.7 80 73 8.3 9.6 8.2 10.6 6.1 6.6 6.1 6.6 1.4 1.4 0.0 0.0 4.0 5.0 10.2 11.2 98 90 11.8 13.7 11.7 15.1 5.0 5.4 5.0 5.4 1.1 1.1 9.7 11.3 9.6 12.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Discontinued - v3.0 49 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 20 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description 1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output Timing1 0.26 0.0 3.7 4.5 4.8 5.2 8.3 8.3 8.3 8.9 0.3 0.0 8.4 11.8 0.03 0.04 0.04 4.3 5.3 5.6 6.0 9.7 9.7 9.7 10.5 0.3 0.0 9.8 13.9 0.035 0.05 0.045 4.9 6.0 6.4 6.9 11.1 11.1 11.1 11.9 0.4 0.0 11.1 15.7 0.04 0.06 0.05 5.8 7.1 7.5 8.1 13.0 13.0 13.0 14.0 0.6 0.0 13.1 18.5 0.05 0.07 0.06 8.3 10.1 10.7 11.5 18.5 18.5 18.5 20.0 0.5 0.0 18.7 26.5 0.07 0.10 0.09 6.8 8.3 8.8 9.5 15.2 15.2 15.2 16.5 ns ns ns ns ns ns ns ns ns ns 15.4 21.7 0.06 0.08 0.07 ns ns ns/pF ns/pF ns CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output 0.26 0.0 4.5 3.7 4.8 5.2 8.3 8.3 8.3 8.9 0.3 0.0 9.9 13.9 0.04 0.04 0.04 5.3 4.3 5.6 6.0 9.7 9.7 9.7 10.5 0.3 0.0 11.6 16.3 0.05 0.045 0.045 6.0 4.9 6.4 6.9 11.1 11.1 11.1 11.9 0.4 0.0 13.2 18.5 0.06 0.05 0.05 5.8 7.1 7.5 8.1 13.0 13.0 13.0 14.0 0.6 0.0 15.5 21.8 0.07 0.06 0.06 8.3 10.1 10.7 11.5 18.5 18.5 18.5 20.0 0.5 0.0 22.3 31.2 0.10 0.09 0.09 6.8 8.3 8.8 9.5 15.2 15.2 15.2 16.5 ns ns ns ns ns ns ns ns ns ns 18.2 25.6 0.08 0.07 0.07 ns ns ns/pF ns/pF ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 50 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 30 0 D X T i m i n g C h a ra c te r i s t i c s (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3 Speed Parameter Description Min. Max. `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Logic Module Propagation Delays Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay 2.2 2.5 2.6 2.9 2.9 3.3 3.4 3.9 4.8 5.6 4.0 4.5 ns ns Predicted Module Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 1.1 1.7 2.4 2.9 5.2 0.6 1.4 2.0 2.8 3.6 6.2 0.7 1.5 2.3 3.1 3.9 7.0 0.8 1.8 2.7 3.7 4.6 8.2 0.9 2.5 3.8 5.2 6.5 10.0 1.3 2.1 3.2 4.3 5.4 9.6 1.0 ns ns ns ns ns ns Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.6 0.0 3.1 3.5 0.32 0.0 2.2 0.75 0.0 3.7 4.1 2.3 2.2 0.4 0.0 2.6 0.9 0.0 4.2 4.7 2.7 2.6 0.42 0.0 3.0 1.0 0.0 4.9 5.5 3.1 2.9 0.5 0.0 3.5 1.4 0.0 7.0 7.9 3.6 3.4 0.7 0.0 5.0 1.1 0.0 5.7 6.4 5.0 4.5 0.6 0.0 4.1 4.2 4.0 ns ns ns ns ns ns ns ns ns Discontinued - v3.0 51 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 30 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3 Speed Parameter Description Min. Max. `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Logic Module Timing Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 6.4 6.4 3.2 3.2 1.5 0.0 0.6 3.2 2.6 0.0 2.6 0.0 7.5 7.5 3.75 3.75 1.8 0.0 0.68 3.75 3.0 0.0 2.3 0.0 8.5 8.5 4.3 4.3 2.0 0.0 0.8 4.3 3.4 0.0 3.5 0.0 10.0 10.0 5.0 5.0 2.4 0.0 0.9 5.0 4.0 0.0 4.1 0.0 14.3 14.3 7.1 7.1 3.4 0.0 1.3 7.1 5.7 0.0 5.9 0.0 11.6 11.6 5.8 5.8 2.82 0.0 1.05 5.8 4.7 0.0 4.8 0.0 ns ns ns ns ns ns ns ns ns ns ns ns Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 8.3 1.5 0.0 0.57 3.2 2.6 0.0 1.1 7.7 9.6 1.8 0.0 0.68 3.75 3.0 0.0 1.35 9.0 11.1 2.0 0.0 0.8 4.3 3.4 0.0 1.5 10.2 13.0 2.4 0.0 0.9 5.0 4.0 0.0 1.8 12.0 18.6 3.4 0.0 1.3 7.1 5.7 0.0 2.6 17.2 15.2 2.8 0.0 1.05 5.8 4.7 0.0 2.1 14.1 ns ns ns ns ns ns ns ns ns 52 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 30 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output1 Input Latch Hold1 0.0 0.45 1 1.4 2.9 0.0 0.5 5.2 1.7 3.4 0.0 0.6 5.9 1.9 3.8 0.0 0.7 6.9 2.2 4.5 0.0 1.0 9.8 3.1 6.4 0.0 0.82 8.1 2.5 5.2 ns ns ns ns ns Input Latch Set-Up1 Latch Active Pulse Width 4.4 Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 1.9 2.5 3.3 3.9 5.0 0.6 2.3 2.9 3.9 4.6 6.0 0.67 2.6 3.3 4.4 5.2 6.7 0.8 3.0 3.9 5.2 6.1 7.9 0.9 4.2 5.5 7.4 8.7 11.2 1.3 3.5 4.6 6.1 7.2 9.2 1.05 ns ns ns ns ns ns Global Clock Network tCKH Input Low to High FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 2.2 2.7 5.5 6.1 154 141 3.0 3.3 3.0 3.3 0.6 0.6 0.0 0.0 2.6 3.2 6.9 7.7 142 130 6.4 7.3 6.6 7.1 3.5 3.8 3.8 3.8 0.75 0.75 0.0 0.0 2.9 3.7 7.4 8.2 123 113 7.6 8.6 7.7 8.4 4.0 4.3 4.0 4.3 0.9 0.9 0.0 0.0 3.4 4.3 9.3 10.2 107 98 8.6 9.7 8.8 9.5 4.7 5.1 4.7 5.1 1.0 1.0 0.0 0.0 4.9 6.1 13.2 14.5 75 69 10.1 11.4 10.3 11.2 6.7 7.2 6.7 7.2 1.4 1.4 0.0 0.0 4.0 5.0 10.9 12.0 91 83 14.4 16.2 14.7 16.0 5.5 6.0 5.5 6.0 1.17 1.17 11.8 13.4 12.1 13.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz tCKL tPWH tPWL Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency tCKSW tSUEXT tHEXT tP fHMAX Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Discontinued - v3.0 53 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s A 3 2 30 0 D X T i m i n g C h a ra c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C) `-3' Speed Parameter Description 1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. 3.3V `Std' Speed Min. Max. Units Min. Max. TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output Timing1 0.26 0.0 3.7 4.4 4.8 5.1 8.3 8.3 4.3 5.4 0.3 0.0 8.4 11.8 0.26 0.32 0.03 4.3 5.2 5.6 6.0 9.75 9.75 5.0 6.3 0.34 0.0 9.7 13.9 0.3 0.37 0.037 4.9 5.9 6.4 6.8 11.1 11.1 5.7 7.1 0.4 0.0 11.1 15.7 0.34 0.4 0.04 5.8 6.9 7.5 8.0 13.0 13.0 6.7 8.4 0.47 0.0 13.1 18.5 0.4 0.5 0.05 7.7 8.1 8.8 9.4 15.2 15.2 7.9 7.9 0.6 0.0 15.4 21.8 0.47 0.58 0.058 8.2 9.8 10.7 11.4 18.5 18.5 9.6 12.0 ns ns ns ns ns ns ns ns ns ns 18.7 26.5 0.6 0.7 0.07 ns ns ns/pF ns/pF ns CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO Data-to-Pad High Data-to-Pad Low Enable-Pad Z to High Enable-Pad Z to Low Enable-Pad High to Z Enable-Pad Low to Z G-to-Pad High G-to-Pad Low I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide-Decode Output 0.26 0.0 4.4 3.7 4.8 5.1 8.3 8.3 4.3 5.4 0.3 0.0 9.9 13.9 0.32 0.26 0.03 5.2 4.3 5.6 6.0 9.75 9.75 5.0 6.3 0.34 0.0 11.6 16.4 0.37 0.3 0.037 5.9 4.9 6.4 6.8 11.1 11.1 5.7 7.1 0.4 0.0 13.2 18.5 0.4 0.3 0.04 6.9 5.8 7.5 8.0 13.0 13.0 6.7 8.4 0.47 0.0 15.5 21.8 0.5 0.4 0.05 8.1 7.7 8.8 9.4 15.2 15.2 7.9 9.9 0.6 0.0 17.6 25.6 0.6 0.5 0.06 8.2 9.8 10.7 11.4 18.5 18.5 9.6 12.0 ns ns ns ns ns ns ns ns ns ns 22.3 31.2 0.10 0.09 0.09 ns ns ns/pF ns/pF ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 54 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P i n D e s c r i p ti o n s CLKA, CLKB Clock A and Clock B (Input) PRB, I/O Probe B (Output) TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground (Input) Input LOW supply voltage. I/O Input/Output (Input, Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. QCLKA,B,C,D Quadrant Clock (Input/Output) I/O pin functions as an input, output, three-state or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the Designer Series software for XL devices and are automatically tristated for DX devices. MODE Mode (Input) These four pins are the quadrant clock inputs. When not used as a register control signal, these pins can function as general purpose I/O. SDO Serial Data (Output) Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is HIGH. This pin functions as an I/O when MODE pin is LOW. SDI Serial Data Input (Input) The MODE pin controls the use of multi-function pins (DCLK, PRA, PRB, SDI, TDO). When the MODE pin is HIGH, the special functions are active. To provide ActionProbe capability, the MODE pin should be terminated to GND through a 10K resistor so the MODE pin can be pulled HIGH when required. NC No Connection Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. TCK Test Clock This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. PRA, I/O Probe A (Output) Clock signal to shift the JTAG data into the device. This pin functions as an I/O when the JTAG fuse is not programmed. TDI Test Data In The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. TDO Test Data Out Serial data output for JTAG instructions and test data. This pin functions as an I/O when the JTAG fuse is not programmed. TMS Test Mode Select Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. V CC Supply Voltage (Input) Input HIGH supply voltage. Note: TCK, TDI, TDO, TMS are only available on devices containing JTAG circuitry. Discontinued - v3.0 55 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s 84-Pin PLCC Package (Top View) 1 84 84-Pin PLCC 56 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 84 -P in P LC C P ac k ag e Pin Number 2 4 5 6 7 8 9 10 12 22 23 28 34 35 36 37 38 39 43 44 45 46 47 49 50 51 52 62 63 64 65 70 76 78 79 80 81 83 84 A1225XL Function CLKB, I/O PRB, I/O I/O GND I/O I/O I/O DCLK, I/O MODE (GND) VCC VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC GND SDI, I/O I/O I/O I/O PRA, I/O CLKA, I/O VCC A1240XL Function CLKB, I/O PRB, I/O I/O GND I/O I/O I/O DCLK, I/O MODE (GND) VCC VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC GND SDI, I/O I/O I/O I/O PRA, I/O CLKA, I/O VCC A3265DX Function CLKB, I/O PRB, I/O I/O (WD) GND I/O I/O (WD) I/O (WD) DCLK, I/O MODE (GND) VCC VCC GND I/O I/O I/O I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O I/O (WD) I/O (WD) GND I/O I/O I/O I/O GND VCC VCC GND SDI, I/O I/O (WD) I/O (WD) I/O (WD) PRA, I/O CLKA, I/O VCC A1280XL Function CLKB, I/O PRB, I/O I/O GND I/O I/O I/O DCLK, I/O MODE (GND) VCC VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC GND SDI, I/O I/O I/O I/O PRA, I/O CLKA, I/O VCC A32100DX Function CLKB, I/O PRB, I/O I/O (WD) GND QCLKC, I/O I/O (WD) I/O (WD) DCLK, I/O MODE (GND) VCC VCC GND TMS, I/O TDI, I/O I/O (WD) QCLKA, I/O I/O (WD) I/O (WD) VCC I/O (WD) QCLKB, I/O I/O (WD) I/O (WD) GND I/O (WD) I/O (WD) SDO, TDO, I/O TCK, I/O GND VCC VCC GND SDI, I/O I/O (WD) I/O (WD) QCLKD, I/O PRA, I/O CLKA, I/O VCC A32140DX Function CLKB, I/O PRB, I/O I/O (WD) GND I/O I/O (WD) I/O (WD) DCLK, I/O MODE (GND) VCC VCC GND TMS, I/O TDI, I/O I/O (WD) I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O (WD) I/O (WD) I/O (WD) GND I/O (WD) I/O (WD) SDO, TDO, I/O TCK, I/O GND VCC VCC GND SDI, I/O I/O (WD) I/O (WD) I/O (WD) PRA, I/O CLKA, I/O VCC Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module 2. Wide-decode I/O (WD) can also be general purpose user I/O. 3. NC: Denotes `No Connection'. 4. All unlisted pin numbers are user I/O's. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. Discontinued - v3.0 57 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s (continued) 100-Pin PQFP Package, 100-Pin VQFP Package (Top View) 100-Pin PQFP 100 1 100 1 100-Pin VQFP 58 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 10 0 -P in P Q F P P a c ka g e, 1 00 -P in V Q FP P a c ka g e A1225XLPQ100 Function DCLK, I/O I/O MODE (GND) I/O GND I/O I/O VCC VCC I/O GND I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O SDO, I/O I/O GND I/O I/O GND VCC VCC VCC I/O GND I/O I/O I/O I/O A1225XLVQ100 Function MODE (GND) I/O I/O GND I/O VCC VCC I/O I/O GND I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O GND I/O GND VCC VCC VCC I/O I/O GND I/O SDI, I/O I/O GND I/O A1240XLPQ100 Function DCLK, I/O I/O MODE (GND) I/O GND I/O I/O VCC VCC I/O GND I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O SDO, I/O I/O GND I/O I/O GND VCC VCC VCC I/O GND I/O I/O I/O I/O A3265DX PQ100 Function DCLK, I/O I/O MODE (GND) I/O GND I/O I/O VCC VCC I/O GND I/O I/O GND I/O (WD) I/O (WD) I/O (WD) I/O (WD) I/O VCC I/O (WD) I/O (WD) I/O (WD) I/O (WD) GND I/O (WD) I/O (WD) I/O I/O SDO, I/O I/O GND I/O I/O GND VCC VCC VCC I/O GND I/O I/O (WD) I/O (WD) I/O (WD) Pin Number 2 3 4 7 9 14 15 16 17 20 22 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 52 55 57 62 63 64 65 66 67 70 72 77 81 82 83 Discontinued - v3.0 59 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F am i l i e s 10 0 -P in P Q F P P a c ka g e, 1 00 -P in V Q FP P a c ka g e A1225XLPQ100 Function GND I/O I/O PRA, I/O I/O CLKA, I/O VCC CLKB, I/O PRB, I/O I/O GND I/O I/O A1225XLVQ100 Function I/O PRA, I/O I/O CLKA, I/O VCC I/O CLKB, I/O PRB, I/O GND I/O I/O I/O DCLK, I/O A1240XLPQ100 Function GND I/O I/O PRA, I/O I/O CLKA, I/O VCC CLKB, I/O PRB, I/O I/O GND I/O I/O A3265DX PQ100 Function GND I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O VCC CLKB, I/O PRB, I/O I/O (WD) GND I/O (WD) I/O (WD) Pin Number 84 85 86 87 88 89 90 92 94 95 96 99 100 Notes: 1. NC: Denotes `No Connection'. 2. All unlisted pin numbers are user I/O's. 3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. 4. I/O (WD): Denotes I/O pin with an associated Wide-Decode Module 60 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P a ck a g e Pi n A s s i g nm en t s (continued) 144-Pin PQFP Package (Top View) 144 1 144-Pin PQFP Discontinued - v3.0 61 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 144-Pin PQFP Package Pin Number 2 9 10 11 18 19 20 21 28 29 30 44 45 46 54 55 64 65 79 80 81 88 89 90 91 92 100 101 102 110 116 117 118 123 A1240XL Function MODE (GND) GND GND GND VCC VCC VCC VCC GND GND GND GND GND GND VCC VCC GND GND GND GND GND GND VCC VCC VCC VCC GND GND GND SDI, I/O GND GND GND PRA, I/O 144-Pin PQFP Package Pin Number 125 126 127 128 130 132 136 137 138 144 A1240XL Function CLKA, I/O VCC VCC VCC CLKB, I/O PRB, I/O GND GND GND DCLK, I/O Notes: 1. NC: Denotes `No Connection'. 2. All unlisted pin numbers are user I/O's. 3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. 62 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P a ck a g e Pi n A s s i g nm en t s (continued) 160-Pin PQFP Package (Top View) 160 1 160-Pin PQFP Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module 2. Wide-Decode I/O (WD) can also be general-purpose user I/O. 3. NC Denotes `No Connection'. 4. All unlisted pin numbers are user I/O's. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. Discontinued - v3.0 63 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F am i l i e s 16 0 -P in P Q F P P a c ka g e Pin Number 2 4 5 6 7 11 12 13 14 16 18 20 21 23 24 25 26 28 29 30 31 33 34 35 36 37 38 40 44 49 54 57 58 59 60 61 62 64 69 80 82 83 84 86 87 88 89 90 A3265DX Function DCLK, I/O I/O I/O (WD) VCC I/O (WD) GND I/O I/O (WD) I/O (WD) PRB, I/O CLKB, I/O VCC CLKA, I/O PRA, I/O I/O I/O (WD) I/O (WD) I/O I/O (WD) GND I/O (WD) I/O I/O (WD) VCC I/O (WD) I/O SDI, I/O GND GND GND VCC VCC VCC GND VCC GND I/O GND GND GND I/O I/O I/O VCC I/O (WD) I/O (WD) GND I/O A1280XL Function DCLK, I/O I/O I/O VCC I/O GND I/O I/O I/O PRB, I/O CLKB, I/O VCC CLKA, I/O PRA, I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O I/O SDI, I/O GND GND GND VCC VCC VCC GND VCC GND I/O GND GND GND I/O I/O I/O VCC I/O I/O GND I/O A32100DX Function DCLK I/O (WD) I/O (WD) VCC I/O GND QCLKC, I/O I/O (WD) I/O (WD) PRB, I/O CLKB, I/O VCC CLKA, I/O PRA, I/O I/O (WD) I/O (WD) I/O QCLKD I/O (WD) GND I/O (WD) NC NC VCC I/O (WD) I/O (WD) SDI, I/O GND GND GND VCC VCC VCC GND VCC GND TCK, I/O GND GND GND SDO, I/O I/O (WD) I/O (WD) VCC I/O I/O (WD) GND I/O (WD) A32140DX Function DCLK, I/O I/O (WD) I/O (WD) VCC I/O GND I/O I/O (WD) I/O (WD) PRB, I/O CLKB, I/O VCC CLKA, I/O PRA, I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) GND I/O (WD) I/O I/O VCC I/O (WD) I/O (WD) SDI, I/O GND GND GND VCC VCC VCC GND VCC GND TCK, I/O GND GND GND SDO, TDO, I/O I/O (WD) I/O (WD) VCC I/O I/O (WD) GND I/O 64 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 16 0 -P in P Q F P P a c ka g e ( C on t in u ed ) Pin Number 91 92 93 95 96 97 98 99 106 107 109 110 111 112 114 115 116 118 119 120 125 130 135 138 139 140 145 150 155 159 160 A3265DX Function I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) VCC GND I/O (WD) I/O (WD) GND I/O I/O (WD) I/O (WD) VCC I/O I/O I/O I/O GND GND GND VCC VCC VCC GND GND VCC GND MODE (GND) GND A1280XL Function I/O I/O I/O I/O I/O I/O VCC GND I/O I/O GND I/O I/O I/O VCC I/O I/O I/O I/O GND GND GND VCC VCC VCC GND GND VCC GND MODE (GND) GND A32100DX Function QCLKB, I/O I/O I/O I/O (WD) I/O (WD) I/O VCC GND I/O (WD) I/O (WD) GND QCLKA, I/O I/O I/O VCC I/O (WD) I/O (WD) TDI, I/O TMS, I/O GND GND GND VCC VCC VCC GND GND VCC GND MODE (GND) GND A32140DX Function I/O I/O I/O I/O I/O (WD) I/O VCC GND I/O (WD) I/O (WD) GND I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O (WD) TDI, I/O TMS, I/O GND GND GND VCC VCC VCC GND GND VCC GND MODE (GND) GND Discontinued - v3.0 65 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s (continued) 208-Pin PQFP Package, 208-Pin RQFP Package (Top View) 208 1 208-Pin PQFP 208-Pin RQFP Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-Decode I/O (WD) can also be general purpose user I/O. 3. NC: Denotes `No Connection'. 4. All unlisted pin numbers are user I/O's. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. 6. RQFP has an exposed circular metal heat sink on the top surface. 66 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 20 8 -P in P Q F P P a c ka g e, 2 08 -P in R Q FP P a c ka g e Pin Number 1 2 3 5 6 7 9 10 11 13 15 16 17 19 20 22 24 26 27 28 29 30 32 33 38 40 41 42 43 45 47 48 50 51 52 53 54 55 57 58 59 60 61 62 65 66 67 68 70 71 74 77 78 A1280XL Function GND NC MODE (GND) I/O I/O I/O NC NC NC I/O I/O NC VCC I/O I/O GND I/O I/O GND VCC VCC I/O VCC I/O I/O I/O NC NC NC I/O I/O I/O NC NC GND GND I/O I/O I/O I/O I/O VCC NC NC I/O I/O NC NC I/O I/O I/O I/O GND A32100DX Function GND VCC MODE (GND) I/O I/O I/O NC NC NC I/O I/O NC VCC I/O I/O GND I/O I/O GND VCC VCC I/O VCC I/O I/O I/O NC NC NC I/O I/O I/O NC NC GND GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) VCC I/O I/O QCLKA, I/O I/O NC I/O I/O (WD) I/O (WD) I/O I/O GND A32140DX Function GND VCC MODE (GND) I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O GND VCC VCC I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O (WD) I/O (WD) I/O VCC I/O I/O I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O GND A32200DXPQ208 Function GND VCC MODE (GND) I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O GND VCC VCC I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O (WD) I/O (WD) I/O VCC I/O I/O QCLKA, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O GND A32200DXRQ208 Function I/O DCLK, I/O I/O I/O (WD) I/O (WD) VCC I/O I/O I/O QCLKC, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) PRB, I/O CLKB, I/O GND VCC I/O CLKA, I/O PRA, I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) I/O I/O VCC I/O (WD) I/O (WD) SDI, I/O I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC VCC A32300DX Function I/O DCLK, I/O I/O I/O (WD) I/O (WD) VCC I/O I/O I/O QCLKC, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) PRB, I/O CLKB, I/O GND VCC I/O CLKA, I/O PRA, I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) I/O I/O VCC I/O (WD) I/O (WD) SDI, I/O I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC VCC Discontinued - v3.0 67 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F am i l i e s 20 8 -P in P Q F P P a c ka g e, 2 08 -P in R Q FP P a c ka g e ( C o n t in ue d ) Pin Number 79 80 81 83 85 86 89 90 91 93 94 95 96 97 98 100 101 103 104 105 106 107 108 110 112 113 114 115 117 121 122 126 127 128 129 130 131 132 133 136 137 138 141 142 144 146 147 148 149 150 151 152 154 A1280XL Function VCC NC I/O I/O I/O I/O NC NC I/O I/O I/O NC NC NC VCC I/O I/O I/O I/O GND NC I/O I/O I/O NC NC NC NC I/O I/O I/O GND I/O I/O GND VCC GND VCC VCC VCC I/O I/O NC I/O I/O NC NC NC NC GND I/O I/O I/O A32100DX Function VCC VCC I/O I/O I/O (WD) I/O (WD) I/O I/O QCLKB, I/O I/O (WD) I/O (WD) I/O NC NC VCC I/O (WD) I/O (WD) SDO, I/O I/O GND VCC I/O I/O I/O NC NC NC NC I/O I/O I/O GND I/O TCK, I/O GND VCC GND VCC VCC VCC I/O I/O I/O I/O I/O NC NC NC NC GND I/O I/O I/O A32140DX Function VCC VCC I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCC I/O (WD) I/O (WD) SDO, TDO, I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND VCC GND VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O A32200DXPQ208 Function VCC VCC I/O I/O I/O (WD) I/O (WD) I/O I/O QCLKB, I/O I/O (WD) I/O (WD) I/O I/O I/O VCC I/O (WD) I/O (WD) SDO, TDO, I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND VCC GND VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O A32200DXRQ208 Function VCC GND TCK, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O SDO, TDO, I/O I/O (WD) I/O (WD) VCC I/O I/O I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) I/O (WD) I/O I/O I/O VCC GND I/O I/O I/O I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKA, I/O I/O I/O I/O VCC I/O I/O (WD) I/O (WD) TDI, I/O A32300DX Function VCC GND TCK, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O SDO, TDO, I/O I/O (WD) I/O (WD) VCC I/O I/O I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) I/O VCC GND I/O I/O I/O I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKA, I/O I/O I/O I/O VCC I/O I/O (WD) I/O (WD) TDI, I/O 68 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 20 8 -P in P Q F P P a c ka g e, 2 08 -P in R Q FP P a c ka g e ( C o n t in ue d ) Pin Number 155 156 157 159 161 162 164 165 166 168 169 171 176 177 178 180 181 182 183 184 186 187 188 190 191 193 194 195 196 197 201 202 203 204 206 207 208 A1280XL Function I/O I/O GND SDI, I/O I/O I/O VCC NC NC I/O I/O NC I/O I/O PRA, I/O CLKA, I/O NC NC VCC GND CLKB, I/O I/O PRB, I/O I/O I/O NC NC NC I/O NC NC VCC I/O I/O I/O DCLK, I/O I/O A32100DX Function I/O I/O GND SDI, I/O I/O (WD) I/O (WD) VCC NC NC I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O I/O VCC VCC GND CLKB I/O PRB, I/O I/O (WD) I/O (WD) I/O NC I/O QCLKC, I/O NC I/O VCC I/O (WD) I/O (WD) I/O DCLK, I/O I/O A32140DX Function I/O I/O GND SDI, I/O I/O (WD) I/O (WD) VCC I/O I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O I/O VCC VCC GND CLKB, I/O I/O PRB, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O I/O VCC I/O (WD) I/O (WD) I/O DCLK, I/O I/O A32200DXPQ208 Function I/O I/O GND SDI, I/O I/O (WD) I/O (WD) VCC I/O I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O I/O VCC VCC GND CLKB, I/O I/O PRB, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) QCLKC, I/O I/O I/O VCC I/O (WD) I/O (WD) I/O DCLK, I/O I/O A32200DXRQ208 Function TMS, I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O VCC VCC I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O MODE VCC GND A32300DX Function TMS, I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O VCC VCC I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O MODE (GND) VCC GND Discontinued - v3.0 69 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s (continued) 240-Pin RQFP Package (Top View) * * * Exposed Heatsink 240 1 * * * 240-Pin RQFP * * * Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-Decode I/O (WD) can also be general purpose user I/O. 3. NC: Denotes `No Connection.' 4. All unlisted pin numbers are user I/O's. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. 6. RQFP has an exposed circular metal heat sink on the top surface. 70 Discontinued - v3.0 * * * I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 24 0 -P in R Q F P P a c ka g e Pin Number 2 6 7 8 15 17 18 21 22 24 26 28 29 30 32 33 34 37 38 45 47 48 52 54 55 57 59 60 61 71 85 88 89 90 91 92 94 108 118 119 A32200DX Function DCLK, I/O I/O (WD) I/O (WD) VCC QCLKC, I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) PRB, I/O CLKB, I/O GND VCC VCC CLKA, I/O I/O PRA, I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O (WD) SDI, I/O VCC GND GND VCC VCC VCC VCC VCC GND TCK, I/O GND VCC VCC GND A32300DX Function DCLK, I/O I/O (WD) I/O (WD) VCC QCLKC, I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) PRB, I/O CLKB, I/O GND VCC VCC CLKA, I/O I/O (WD) PRA, I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O (WD) SDI, I/O VCC GND GND VCC VCC VCC VCC VCC GND TCK, I/O GND VCC VCC GND Pin Number 120 121 123 125 126 128 132 133 135 142 143 147 148 150 151 152 159 160 163 164 166 172 174 175 178 179 180 181 182 192 206 209 210 219 227 237 238 239 240 A32200DX Function GND GND SDO, TDO, I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) I/O (WD) I/O I/O VCC VCC GND I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKA, I/O VCC I/O (WD) I/O (WD) TDI, I/O TMS, I/O GND VCC GND VCC VCC VCC VCC VCC VCC GND MODE (GND) VCC GND A32300DX Function GND GND SDO, TDO, I/O I/O (WD) I/O (WD) VCC I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) VCC VCC GND I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKA, I/O VCC I/O (WD) I/O (WD) TDI, I/O TMS, I/O GND VCC GND VCC VCC VCC VCC VCC VCC GND MODE (GND) VCC GND Discontinued - v3.0 71 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s (continued) 176-Pin TQFP Package (Top View) 176 1 176-Pin TQFP Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-Decode I/O (WD) can also be general-purpose user I/O. 3. NC: Denotes `No Connection.' 4. All unlisted pin numbers are user I/O's. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND. 72 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 17 6 -p in T Q FP P ac k ag e Pin Number 1 2 8 10 11 13 18 19 20 22 23 24 25 26 27 28 29 33 37 38 45 46 47 48 49 50 51 52 54 55 56 57 59 60 61 64 66 67 68 69 70 72 73 74 75 76 77 78 79 80 A1240XL Function GND MODE NC NC NC NC GND NC NC NC GND NC VCC NC NC VCC NC NC NC NC GND I/O I/O I/O I/O I/O I/O NC NC NC I/O NC I/O I/O NC NC NC GND VCC I/O I/O I/O I/O NC I/O I/O NC NC I/O NC A3265DX Function GND MODE NC NC NC VCC GND I/O I/O I/O GND VCC VCC I/O I/O VCC NC NC NC NC GND I/O I/O NC I/O I/O I/O VCC I/O (WD) I/O (WD) I/O NC I/O (WD) I/O (WD) I/O I/O I/O GND VCC I/O (WD) I/O (WD) I/O I/O (WD) NC I/O (WD) I/O NC NC I/O I/O (WD) A1280XL Function GND MODE NC I/O I/O VCC GND I/O I/O I/O GND VCC VCC I/O I/O VCC I/O NC I/O NC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O NC I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O A32100DX Function GND MODE NC I/O I/O VCC GND I/O I/O I/O GND VCC VCC I/O I/O VCC I/O NC I/O NC GND TMS, I/O TDI, I/O I/O I/O I/O (WD) I/O (WD) VCC I/O I/O I/O QCLKA, I/O I/O (WD) I/O (WD) I/O I/O I/O GND VCC I/O I/O I/O (WD) I/O (WD) I/O I/O QCLKB, I/O I/O I/O (WD) I/O (WD) NC A32140DX Function GND MODE I/O I/O I/O VCC GND I/O I/O I/O GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) I/O VCC I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O I/O GND VCC I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O Discontinued - v3.0 73 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F am i l i e s 17 6 -p in T Q FP P ac ka g e ( C o n t in ue d ) Pin Number 81 82 84 85 86 87 89 96 97 101 103 106 107 108 109 110 111 112 113 114 115 116 117 121 124 125 126 133 135 136 137 138 139 140 141 142 143 144 145 146 147 149 150 151 152 154 155 156 158 160 A1240XL Function I/O NC I/O I/O NC I/O GND NC NC NC NC GND NC NC GND VCC GND VCC VCC NC NC NC I/O NC NC NC NC GND SDI, I/O NC I/O I/O I/O NC I/O I/O NC NC NC I/O NC I/O I/O NC PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O A3265DX Function I/O (WD) VCC I/O I/O NC I/O GND NC I/O NC I/O GND I/O I/O GND VCC GND VCC VCC I/O I/O VCC NC NC NC NC NC GND SDI, I/O NC I/O I/O I/O (WD) VCC I/O (WD) I/O I/O I/O (WD) NC I/O (WD) I/O I/O (WD) I/O (WD) I/O PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O A1280XL Function I/O VCC I/O I/O I/O I/O GND I/O I/O NC I/O GND I/O I/O GND VCC GND VCC VCC I/O I/O VCC I/O NC I/O I/O NC GND SDI, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O A32100DX Function I/O VCC I/O (WD) I/O (WD) I/O SDO, TDO, I/O GND I/O I/O NC I/O GND I/O TCK, I/O GND VCC GND VCC VCC I/O I/O VCC I/O I/O I/O I/O NC GND SDI, I/O I/O I/O (WD) I/O (WD) I/O VCC I/O I/O (WD) I/O (WD) I/O NC QCLKD, I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O A32140DX Function I/O VCC I/O (WD) I/O (WD) I/O SDO, TDO, I/O GND I/O I/O I/O I/O GND I/O TCK, I/O GND VCC GND VCC VCC I/O I/O VCC I/O I/O I/O I/O I/O GND SDI, I/O I/O I/O (WD) I/O (WD) I/O VCC I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O 74 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 17 6 -p in T Q FP P ac k ag e ( C o n t in ue d ) Pin Number 161 162 163 164 165 166 168 169 170 171 172 173 175 A1240XL Function NC I/O I/O I/O NC NC NC I/O NC I/O I/O NC DCLK, I/O A3265DX Function I/O I/O (WD) I/O (WD) I/O NC I/O I/O I/O (WD) VCC I/O (WD) I/O NC DCLK, I/O A1280XL Function I/O I/O I/O I/O NC I/O I/O I/O VCC I/O I/O I/O DCLK, I/O A32100DX Function I/O (WD) I/O (WD) I/O QCLKC, I/O NC I/O I/O I/O VCC I/O (WD) I/O (WD) I/O DCLK, I/O A32140DX Function I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O VCC I/O (WD) I/O (WD) I/O DCLK, I/O Discontinued - v3.0 75 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s (continued) 100-Pin CPGA (Top View) 1 A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 A B C D E 100-Pin CPGA F G H J K L 2 3 4 5 6 7 8 9 10 11 Orientation Pin Signal PRA or I/O PRB or I/O MODE SDI or I/O DCLK or I/O CLKA or I/O CLKB or I/O GND VCC Pad Number 85 92 2 77 100 87 90 7, 20, 32, 44, 55, 70, 82, 94 15, 38, 64, 88 Location A7 A4 C2 C8 C3 C6 D6 E3, G3, J5, J7, G9, F11, D10, C7, C5 F3, G1, K6, F9, F10, E11, B6 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven LOW. All unassigned pins are available for use as I/Os. MODE = GND, except during device programming or debugging. 76 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P a ck a g e Pi n A s s i g nm en t s (continued) 132-Pin CPGA (Top View) 1 A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F 132-Pin CPGA G H J K L M N 2 3 4 5 6 7 8 9 10 11 12 13 Orientation Pin Signal PRA or I/O PRB or I/O MODE SDI or I/O DCLK or I/O CLKA or I/O CLKB or I/O GND VCC Pad Number 113 121 2 101 132 115 119 9, 10, 26, 27, 41, 58, 59, 73, 74, 92, 93, 107, 108, 125, 126 18, 19, 49, 50, 83, 84, 116, 117 Location B8 C6 A1 B12 C3 B7 B6 E3, F4, J2, J3, L5, L9, M9, K12, J11, H13, E12, E11, C9, B9, B5, C5 G3, G2, G4, L7, K7, G10, G11, G12, G13, D7, C7 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven LOW. All unassigned pins are available for use as I/Os. MODE = GND, except during device programming or debugging. Discontinued - v3.0 77 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P ac k a g e Pi n A s s i g nm en t s (continued) 176-Pin CPGA (Top View) 1 A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G 176-Pin CPGA H J K L M N P R 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signal PRA or I/O PRB or I/O MODE SDI or I/O DCLK or I/O CLKA or I/O CLKB or I/O GND VCC Pad Number 152 160 2 135 175 154 158 1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89 101, 106, 111, 121, 126, 133, 145, 156, 165 13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170 Location C9 D7 C3 B14 B3 A9 B8 D4, E4, G4, H4, K4, L4, M4, M6, M8, M10, M12 K12, J12, J13, H12, F12, E12, D12, D10, C8, D6 F4, H2, H3, J4, M5, N8, M11, J14, H13, H14, G12, D11, D8, D5 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven LOW. All unassigned pins are available for use as I/Os. MODE = GND, except during device programming or debugging. 78 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P a ck a g e Pi n A s s i g nm en t s (continued) 84 -P in C Q FP 84 Pin #1 Index 1 84-Pin CQFP Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven LOW. All unassigned pins are available for use as I/Os. MODE = GND, except during device programming or debugging. Discontinued - v3.0 79 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s 84 -p in C Q F P P ac k ag e Pin Number 1 2 7 10 11 12 17 22 23 24 25 26 28 30 32 33 34 35 36 37 38 39 40 41 42 43 50 51 52 53 55 56 59 63 64 65 66 67 68 69 70 71 72 73 A32100DX Function GND MODE (GND) VCC GND VCC VSV (VCC) GND GND TMS, I/O TDI, I/O I/O (WD) I/O (WD) QCLKA, I/O I/O (WD) GND VCC I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) GND I/O (WD) I/O (WD) I/O (WD) SDO, I/O GND GND TCK, I/O VKS (GND) VPP (VCC) VSV (VCC) VCC GND GND SDI I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O 8 4- pi n C Q F P P a ck a ge Pin Number 74 76 77 78 79 80 81 82 83 84 A32100DX Function VCC CLKB, I/O PRB, I/O I/O (WD) I/O (WD) QCLKC, I/O GND I/O (WD) I/O (WD) DCLK, I/O 80 Discontinued - v3.0 I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s P a ck a g e Pi n A s s i g nm en t s (continued) 17 2 -P in C Q F P 172 Pin #1 Index 1 172-Pin CQFP Signal CLKA or I/O CLKB or I/O DCLK or I/O GND MODE PRA or I/O PRB or I/O SDI or I/O VCC Pad Number 150 154 171 7, 17, 22, 32, 37, 55, 65, 75, 98, 103, 106, 118, 123, 141, 152, 161 1 148 156 131 12, 23, 24, 27, 50, 66, 80, 107, 109, 110, 113, 136, 151, 166 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven LOW. All unassigned pins are available for use as I/Os. MODE = GND, except during device programming or debugging. Discontinued - v3.0 81 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s L i s t o f C ha n g es The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (v3.0) Because the changes in this data sheet are extensive and technical in nature--due to the elimination of 32400DX product--this should be viewed as a new document. Please read it as you would a data sheet that is published for the first time. Note that the "Package and Mechanical Drawings" section has been eliminated from the data sheet and can now be found on the Actel web site. Note that the "Package Characteristics and Mechanical Drawings" section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site. Page ALL Unspecified D a ta S h e e t C at e g or i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. These data sheets are marked as "Advanced" or Preliminary" data sheets. The definition of these categories are as follows: A d v an ce d The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P r e li mi na r y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. U n ma r k ed ( pr o d uc t io n ) The data sheet contains information that is considered to be final. 82 Discontinued - v3.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44 (0)1256 305600 Fax: +44 (0)1256 355420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 5172135-1/2.01 I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F am i l i e s 84 Discontinued - v3.0 |
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